JAJSFZ3C January 2011 – August 2018 TCA4311A
PRODUCTION DATA.
Once connection has been established, rise-time accelerator circuits on all four SDA and SCL pins are activated. These allow the user to choose weaker DC pull-up currents on the bus, reducing power consumption while still meeting system rise-time requirements. During positive bus transitions, the TCA4311A switches in 2 mA (typical) of current to quickly slew the SDA and SCL lines once their DC voltages exceed 0.6 V. Using a general rule of 20 pF of capacitance for every device on the bus (10 pF for the device and 10 pF for interconnect), choose a pull-up current so that the bus will rise on its own at a rate of at least 1.25 V/μs to specify activation of the accelerators.
For example, assume an SMBus system with VCC = 3 V, a 10-kΩ pull-up resistor and equivalent bus capacitance of 200 pF. The rise-time of an SMBus system is calculated from (VIL(MAX) – 0.15 V) to (VIH(MIN) + 0.15 V), or 0.65 V to 2.25 V. It takes an RC circuit 0.92 time constants to traverse this voltage for a 3 V supply; in this case, 0.92 × (10 kΩ × 200 pF) = 1.84 μs. Thus, the system exceeds the maximum allowed rise-time of 1 μs by 84%. However, using the rise-time accelerators, which are activated at a DC threshold of below 0.65 V, the worst-case rise-time is: (2.25 V – 0.65 V) × 200 pF/1 mA = 320 ns, which meets the 1 μs rise-time requirement.