9.2.1.2 Propagation Delays

During a rising edge, the rise-time on each side is determined by the combined pull-up current of the TCA4311A boost current and the bus resistor and the equivalent capacitance on the line. If the pull-up currents are the same, a difference in rise-time occurs which is directly proportional to the difference in capacitance between the two sides. This effect is displayed in Figure 10 for V_CC = 3.3 V and a 10-kΩ pull-up resistor on each side (50 pF on one side and 150 pF on the other). Since the output side has less capacitance than the input, it rises faster and the effective t_PLH is negative.

There is a finite propagation delay, t_PHL, through the connection circuitry for falling waveforms. Figure 11 shows the falling edge waveforms for the same V_CC, pull-up resistors and equivalent capacitance conditions as used in Figure 10. An external NMOS device pulls down the voltage on the side with 150 pF capacitance; the TCA4311A pulls down the voltage on the opposite side, with a delay of 55 ns. This delay is always positive and is a function of supply voltage, temperature and the pull-up resistors and equivalent bus capacitances on both sides of the bus. The Typical Characteristics section shows t_PHL as a function of temperature and voltage for 10-kΩ pull-up resistors and 100 pF equivalent capacitance on both sides of the part. By comparison with Figure 11, the V_CC = 3.3 V curve shows that increasing the capacitance from 50 pF to 100 pF results in a t_PHL increase from 55 ns to 75 ns. Larger output capacitances translate to longer delays (up to 150 ns). Users must quantify the difference in propagation times for a rising edge versus a falling edge in their systems and adjust setup and hold times accordingly.