The TFP401A-Q1 device receives a clock reference from the DVI transmitter that has a period equal to the pixel time, t_pix. Another name for the frequency of this clock is the pixel rate. Because the TMDS encoded data on Rx[2:0] contains 10 bits per 8-bit pixel, it follows that the Rx[2:0] serial bit rate is 10 times the pixel rate. For example, the required pixel rate to support a UXGA resolution with 60-Hz refresh rate is 165 MHz. The TMDS serial bit rate is 10× the pixel rate, or 1.65 Gb/s. Due to the transmission of this high-speed digital bit stream, on three separate channels (or twisted-pair wires) of long distances (3–5 meters), there is no assurance of phase synchronization between the data steams and the input reference clock. In addition, skew between the three data channels is common. The TFP401A-Q1 device uses a 4× oversampling scheme of the input data streams to achieve reliable synchronization with up to 1-t_pix channel-to-channel skew tolerance. Accumulated jitter on the clock and data lines due to reflections and external noise sources is also typical of high-speed serial data transmission; hence, the TFP401A-Q1 design for high jitter tolerance.

A phase-locked loop (PLL) conditions the input clock of the TFP401A-Q1 device to remove high-frequency jitter from the clock. The PLL provides four 10× clock outputs of different phase to locate and sync the TMDS data streams (4× oversampling). During active display, the pixel data encoding is for transition minimization, whereas in blank, the control data encoding is for transition maximization. Transmitting in blank for a minimum period of time, 128 t_pix, requires a DVI-compliant transmitter to ensure sufficient time for data synchronization when the receiver sees a transition-maximized code. Synchronization during blank, when the data is transition-maximized, ensures reliable data-bit boundary detection. Phase synchronization to the data streams, maintained as long as the link remains active, is unique for each of the three input channels.