JAJSJN1A May   2023  – September 2023 TMP4718

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Interface Timing
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 1.2-V Logic Compatible Inputs
      2. 8.3.2 Series Resistance Cancellation
      3. 8.3.3 Device Initialization, Resistor Decoding, and Default Temperature Conversion
      4. 8.3.4 Adjustable Default T_CRIT High-Temperature Limit
      5. 8.3.5 ALERT and T_CRIT Output
      6. 8.3.6 Fault Queue
      7. 8.3.7 Filtering
      8. 8.3.8 One-Shot Conversions
    4. 8.4 Device Functional Modes
      1. 8.4.1 Interrupt and Comparator Mode
        1. 8.4.1.1 Interrupt Mode
        2. 8.4.1.2 Comparator Mode
        3. 8.4.1.3 T_CRIT Output
      2. 8.4.2 Shutdown Mode
      3. 8.4.3 Continuous Conversion Mode
    5. 8.5 Programming
      1. 8.5.1 Temperature Data Format
      2. 8.5.2 I2C and SMBus Interface
      3. 8.5.3 Device Address
      4. 8.5.4 Bus Transactions
        1. 8.5.4.1 Writes
        2. 8.5.4.2 Reads
      5. 8.5.5 SMBus Alert Mode
    6. 8.6 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6 I2C Interface Timing

minimum and maximum specifications are over –40 °C to 125 °C and VDD = 1.62 V to 5.5 V (unless otherwise noted)(1)
STANDARD MODE FAST MODE FAST MODE PLUS UNIT
MIN MAX MIN MAX MIN MAX
f(SCL) SCL operating frequency(2) 1 100 1 400 1 1000 kHz
t(BUF) Bus-free time between STOP and START conditions 4.7 – 1.3 – 0.5 – µs
t(SUSTA) Repeated START condition setup time 4.7 – 0.6 – 0.26 – µs
t(HDSTA) Hold time after repeated START condition.
After this period, the first clock is generated.		 4.0 – 0.6 – 0.26 – µs
t(SUSTO) STOP condition setup time 4.0 – 0.6 – 0.26 – µs
t(HDDAT) Data hold time(3) 0 3450 0 900 0 150 ns
t(SUDAT) Data setup time 250 – 100 – 50 – ns
t(LOW) SCL clock low period 4.7 – 1.3 – 0.5 – µs
t(HIGH) SCL clock high period 4.0 – 0.6 – 0.26 – µs
t(VDAT) Data valid time (data response time)(4) – 3.45 0.9 – 0.45 µs
tR Clock and data rise time – 1000 20 300 – 120 ns
tF Clock and fall time – 300 20 ×
(VDD / 5.5 V)		 300 20 ×
(VDD / 5.5 V)		 120 ns
ttimeout Timeout (SCL = GND) 20 30 20 30 20 30 ms
(1) The controller and target have the same I/O supply value. Values are based on statistical analysis of samples tested during initial release.
(2) The TMP4718 is equipped with a 50-ns spike filter on both SCL and SDA lines. The filter allows the device to be used alongside I3C devices without impacting the communcation.
(3) The maximum t(HDDAT) can be 3.45 µs and 0.9 µs for Standard Mode and Fast Mode, but must be less than the maximum of t(VDAT) by a transition time.
(4) t(VDAT) = time for data signal from SCL LOW to SDA output (HIGH to LOW, depending on which is worse).