JAJSHU2A August   2019  – July 2020 TMUX1208-Q1

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics (VDD = 5 V ±10 %)
    6. 6.6 Electrical Characteristics (VDD = 3.3 V ±10 %)
    7. 6.7 Electrical Characteristics (VDD = 1.8 V ±10 %)
    8. 6.8 Electrical Characteristics (VDD = 1.2 V ±10 %)
  7. Parameter Measurement Information
    1. 7.1  On-Resistance
    2. 7.2  Off-Leakage Current
    3. 7.3  On-Leakage Current
    4. 7.4  Transition Time
    5. 7.5  Break-Before-Make
    6. 7.6  tON(EN) and tOFF(EN)
    7. 7.7  Charge Injection
    8. 7.8  Off Isolation
    9. 7.9  Crosstalk
    10. 7.10 Bandwidth
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bidirectional Operation
      2. 8.3.2 Rail to Rail Operation
      3. 8.3.3 1.8 V Logic Compatible Inputs
      4. 8.3.4 Fail-Safe Logic
      5. 8.3.5 Device Functional Modes
      6. 8.3.6 Truth Tables
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Layout Information
      2. 10.1.2 41
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
  12. 12Electrostatic Discharge Caution
  13. 13Glossary

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Device Functional Modes

When the EN pin of the TMUX1208-Q1 is pulled high, one of the switches is closed based on the state of the address lines. When the EN pin is pulled low, all the switches are in an open state regardless of the state of the address lines.

The TMUX1208-Q1 can be operated without any external components except for the supply decoupling capacitors. Unused logic control pins should be tied to GND or VDD in order to ensure the device does not consume additional current as highlighted in Implications of Slow or Floating CMOS Inputs. Unused signal path inputs (Sx or D) should be connected to GND.