JAJSNZ7A October   2022  – November 2022 TMUX7436F

PRODMIX  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Thermal Information
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Electrical Characteristics: Global
    6. 6.6  ±15 V Dual Supply: Electrical Characteristics
    7. 6.7  ±20 V Dual Supply: Electrical Characteristics
    8. 6.8  12 V Single Supply: Electrical Characteristics
    9. 6.9  36 V Single Supply: Electrical Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1  On-Resistance
    2. 7.2  Off-Leakage Current
    3. 7.3  On-Leakage Current
    4. 7.4  Input and Output Leakage Current Under Overvoltage Fault
    5. 7.5  Enable Delay Time
    6. 7.6  Break-Before-Make Delay
    7. 7.7  Transition Time
    8. 7.8  Fault Response Time
    9. 7.9  Fault Recovery Time
    10. 7.10 Fault Flag Response Time
    11. 7.11 Fault Flag Recovery Time
    12. 7.12 Charge Injection
    13. 7.13 Off Isolation
    14. 7.14 Crosstalk
    15. 7.15 Bandwidth
    16. 7.16 THD + Noise
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Flat ON-Resistance
      2. 8.3.2 Protection Features
        1. 8.3.2.1 Input Voltage Tolerance
        2. 8.3.2.2 Powered-Off Protection
        3. 8.3.2.3 Fail-Safe Logic
        4. 8.3.2.4 Overvoltage Protection and Detection
        5. 8.3.2.5 Adjacent Channel Operation During Fault
        6. 8.3.2.6 ESD Protection
        7. 8.3.2.7 Latch-Up Immunity
        8. 8.3.2.8 EMC Protection
      3. 8.3.3 Overvoltage Fault Flags
      4. 8.3.4 Bidirectional Operation
      5. 8.3.5 1.8 V Logic Compatible Inputs
      6. 8.3.6 Integrated Pull-Down Resistor on Logic Pins
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Mode
      2. 8.4.2 Fault Mode
      3. 8.4.3 Truth Tables
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PW|16
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

Figure 5-1 PW Package,
16-Pin TSSOP (Top View)
Figure 5-2 RRP (Preview) Package,
16-Pin WQFN (Top View)
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME TSSOP WQFN(2)
D1 3 1 I/O Drain pin 1. Can be an input or output. The drain pin is not overvoltage protected.
D2 11 9 I/O Drain pin 2. Can be an input or output. The drain pin is not overvoltage protected.
DR 8 5 I Drain Response (DR) input. Tying the DR pin to GND enables the drain to be pulled to VDD or VSS through a 40 kΩ resistor during an overvoltage fault event. The drain pin becomes open circuit when the DR pin is a logic high or left floating.
EN 14 12 I Active high logic enable (EN) pin, has internal 4 MΩ pull-down resistor. The device is disabled and all switches become high impedance when the pin is low. As provided in Table 8-1, when the pin is high, the SELx logic inputs determine individual switch states.
FF 15 13 O General fault flag. This pin is an open drain output and is asserted low when overvoltage condition is detected on any of the source (Sxy) input pins. Connect this pin to an external supply (1.8 V to 5.5 V) through a 1 kΩ pull-up resistor.
GND 6 4 P Ground (0 V) reference
N.C. 7 7 — No internal connection. This pin can be shorted to GND or left floating.
S1A 2 16 I/O Overvoltage protected source pin 1A. Can be an input or output.
S1B 4 2 I/O Overvoltage protected source pin 1B. Can be an input or output.
S2A 10 8 I/O Overvoltage protected source pin 2A. Can be an input or output.
S2B 12 10 I/O Overvoltage protected source pin 2B. Can be an input or output.
SEL1 1 15 I Logic control input 1.
SEL2 9 6 I Logic control input 2.
SF 16 14 O

Specific fault flag. This pin is an open drain output and is asserted low when an overvoltage condition is detected on a specific (Sxy) input pin, depending on the state of the SELx pins, as provided in Table 8-1. Connect this pin to an external supply (1.8 V to 5.5 V) through a 1 kΩ pull-up resistor.
VDD 13 11 P Positive power supply. This pin is the most positive power-supply potential. Connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND for reliable operation.
VSS 5 3 P Negative power supply. This pin is the most negative power-supply potential. This pin can be connected to ground in single-supply applications. Connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND for reliable operation.
Thermal Pad — The thermal pad is not connected internally. It is recommended to tie the pad to GND or VSS for best performance.
(1) I = input, O = output, I/O = input and output, P = power.
(2) Preview package.