JAJSN99A December   2022  – September 2023 TPS25772-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Recommended Components
    5. 7.5  Thermal Information
    6. 7.6  Buck-Boost Regulator
    7. 7.7  CC Cable Detection Parameters
    8. 7.8  CC VCONN Parameters
    9. 7.9  CC PHY Parameters
    10. 7.10 Thermal Shutdown Characteristics
    11. 7.11 Oscillator Characteristics
    12. 7.12 ADC Characteristics
    13. 7.13 TVS Parameters
    14. 7.14 Input/Output (I/O) Characteristics
    15. 7.15 BC1.2 Characteristics
    16. 7.16 I2C Requirements and Characteristics
    17. 7.17 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Device Power Management and Supervisory Circuitry
        1. 9.3.1.1 VIN UVLO and Enable/UVLO
        2. 9.3.1.2 Internal LDO Regulators
      2. 9.3.2  TVSP Device Configuration and ESD Protection
      3. 9.3.3  Buck-Boost Regulator
        1. 9.3.3.1  Buck-Boost Regulator Operation
        2. 9.3.3.2  Switching Frequency, Frequency Dither, Phase-Shift and Synchronization
        3. 9.3.3.3  VIN Supply and VIN Over-Voltage Protection
        4. 9.3.3.4  Feedback Paths and Error Amplifiers
        5. 9.3.3.5  Transconductors and Compensation
        6. 9.3.3.6  Output Voltage DAC, Soft-Start and Cable Droop Compensation
        7. 9.3.3.7  VBUS Overvoltage Protection
        8. 9.3.3.8  VBUS Undervoltage Protection
        9. 9.3.3.9  Current Sense Resistor (RSNS) and Current Limit Operation
        10. 9.3.3.10 Buck-Boost Peak Current Limits
      4. 9.3.4  USB-PD Physical Layer
        1. 9.3.4.1 USB-PD Encoding and Signaling
        2. 9.3.4.2 USB-PD Bi-Phase Marked Coding
        3. 9.3.4.3 USB-PD Transmit (TX) and Receive (Rx) Masks
        4. 9.3.4.4 USB-PD BMC Transmitter
        5. 9.3.4.5 USB-PD BMC Receiver
        6. 9.3.4.6 Squelch Receiver
      5. 9.3.5  VCONN
      6. 9.3.6  Cable Plug and Orientation Detection
        1. 9.3.6.1 Configured as a Source
        2. 9.3.6.2 Configured as a Sink
        3. 9.3.6.3 Overvoltage Protection (Px_CC1, Px_CC2)
      7. 9.3.7  ADC
        1. 9.3.7.1 ADC Divider Ratios
      8. 9.3.8  BC 1.2, Legacy and Fast Charging Modes (Px_DP, Px_DM)
      9. 9.3.9  USB2.0 Low-Speed Endpoint
      10. 9.3.10 Digital Interfaces
        1. 9.3.10.1 General GPIO
        2. 9.3.10.2 I2C Buffer
      11. 9.3.11 I2C Interface
        1. 9.3.11.1 I2C Interface Description
        2. 9.3.11.2 I2C Clock Stretching
        3. 9.3.11.3 I2C Address Setting
        4. 9.3.11.4 Unique Address Interface
        5. 9.3.11.5 I2C Pullup Resistor Calculation
      12. 9.3.12 Digital Core
        1. 9.3.12.1 Device Memory
        2. 9.3.12.2 Core Microprocessor
      13. 9.3.13 NTC Input
      14. 9.3.14 Thermal Sensors and Thermal Shutdown
    4. 9.4 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Application GUI Selections
        2. 10.2.2.2 EEPROM Selection
        3. 10.2.2.3 EN/UVLO
        4. 10.2.2.4 Sense Resistor, RSNS, RCSP, RCSN and CFILT
        5. 10.2.2.5 Inductor Currents
        6. 10.2.2.6 Output Capacitor
        7. 10.2.2.7 Input Capacitor
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.1 Overview

The TPS25772-Q1 is a fully-integrated AEC-Q100 USB Power Delivery (USB-PD) source intended for use in 12-V automotive battery systems. Input supply pin, VIN, must be connected to a load dump clamped battery supply, VBAT, and never exceed 40 V (ABS MAX).

The device consists of seven sub-blocks: USB-PD controller; Type-C cable plug and orientation detection circuitry; USB Endpoint; USB Battery Charging Specification Version 1.2 (BC1.2) detection circuitry; digital core; device power management and supervisory circuitry; and a buck-boost converter integrated with 4 power switches.

The USB-PD controller provides the physical layer (PHY) functionality of the USB-PD protocol. The USB-PD data is output through either the Px_CC1 pin or the Px_CC2 pin, depending on the orientation of the reversible USB Type-C cable. For a high-level block diagram of the USB-PD physical layer, a description of its features and more detailed circuitry, see USB-PD Physical Layer.

The cable plug and orientation detection analog circuitry automatically detects a USB Type-C cable plug insertion and also automatically detects the cable orientation. For a high-level block diagram of cable plug and orientation detection, a description of its features and more detailed circuitry, see Cable Plug and Orientation Detection.

A USB Endpoint is included for downloading configuration information and firmware updates. When enabled by firmware, the USB Endpoint connects to the Port A DP and DM pins.

The USB BC1.2 sub-block contains circuitry to support legacy USB charging methods which signal on the USB DP and DM data lines including: DCP, Divider-3, 1.2 V mode, and HVDCP. See BC 1.2, legacy and fast charging modes (Px_DP, Px_DM).

The power management and supervisory circuitry generates the LDO_5V, LDO_3V3, and LDO_1V5 voltage rails used by the device. LDO_5V supplies the LDO_3V3 and LDO_1V5 rails. For a high-level block diagram of the power management circuitry, a description of its features and more detailed operation, see Internal LDO Regulators section.

The digital core contains an ARM Cortex-M0 with 160-kB ROM and 27-kB RAM memory. The ROM contains firmware code to execute device functionality. RAM stores application configuration code created using the Graphical User Interface (GUI) and post-manufacturing firmware updates. The digital core is the engine for autonomously managing the system including: USB port connection status and communication; system power budget and allocation; system thermal monitoring and load shedding; and fault detection and reporting. All devices contain one controller I2C port (I2C1) for controlling external peripherals such as external EEPROM memory; DC/DC converters; USB data multiplexers/redrivers; GPIO expanders; and additional temperature sensors. Some devices include an I2C target port (I2C2) for connection to an external processor, HUB or embedded controller. An integrated 8-bit analog-to-digital converter ADC (see the ADC section), monitors USB port telemetry information. USB port connection status, voltage, current and fault information can be read from I2C2 target port. For a high-level block diagram of the digital core and a description of its features, see the Digital Core section.

The integrated buck-boost converter is the PA_VBUS power source. It operates in buck mode when VIN is greater than VOUT and boost mode when VIN is less than VOUT. When VIN and VOUT are nearly the same, it operates in transition mode.

Dual Port Devices

TPS25772-Q1 is a dual USB port device. Refer to Device Comparison Table for functional differences. The TPS25772-Q1 consists of a single 3 to 21 V output internal buck-boost converter, two USB-PD port controllers providing cable plug and orientation detection, two internal VCONN source paths, legacy USB Battery Charging Specification v1.2 Dedicated Charging Port (DCP) as well as legacy (non-USB compliant) charger detection including: Divider-3, 1.2 V, and HVDCP modes on each port.

PB_VBUS for TPS25772-Q1 must be supplied from an external power source. The implementation of this power is shown in Table 9-1.

Table 9-1 Supported Dual USB Port Implementations
Port A (PA) Port B (PB) Port B (PB) Suggested Power Devices
USB Power Delivery (including PPS) Type-C with USB Power Delivery (including PPS) TPS55288-Q1