JAJSN99A December   2022  – September 2023 TPS25772-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Recommended Components
    5. 7.5  Thermal Information
    6. 7.6  Buck-Boost Regulator
    7. 7.7  CC Cable Detection Parameters
    8. 7.8  CC VCONN Parameters
    9. 7.9  CC PHY Parameters
    10. 7.10 Thermal Shutdown Characteristics
    11. 7.11 Oscillator Characteristics
    12. 7.12 ADC Characteristics
    13. 7.13 TVS Parameters
    14. 7.14 Input/Output (I/O) Characteristics
    15. 7.15 BC1.2 Characteristics
    16. 7.16 I2C Requirements and Characteristics
    17. 7.17 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Device Power Management and Supervisory Circuitry
        1. 9.3.1.1 VIN UVLO and Enable/UVLO
        2. 9.3.1.2 Internal LDO Regulators
      2. 9.3.2  TVSP Device Configuration and ESD Protection
      3. 9.3.3  Buck-Boost Regulator
        1. 9.3.3.1  Buck-Boost Regulator Operation
        2. 9.3.3.2  Switching Frequency, Frequency Dither, Phase-Shift and Synchronization
        3. 9.3.3.3  VIN Supply and VIN Over-Voltage Protection
        4. 9.3.3.4  Feedback Paths and Error Amplifiers
        5. 9.3.3.5  Transconductors and Compensation
        6. 9.3.3.6  Output Voltage DAC, Soft-Start and Cable Droop Compensation
        7. 9.3.3.7  VBUS Overvoltage Protection
        8. 9.3.3.8  VBUS Undervoltage Protection
        9. 9.3.3.9  Current Sense Resistor (RSNS) and Current Limit Operation
        10. 9.3.3.10 Buck-Boost Peak Current Limits
      4. 9.3.4  USB-PD Physical Layer
        1. 9.3.4.1 USB-PD Encoding and Signaling
        2. 9.3.4.2 USB-PD Bi-Phase Marked Coding
        3. 9.3.4.3 USB-PD Transmit (TX) and Receive (Rx) Masks
        4. 9.3.4.4 USB-PD BMC Transmitter
        5. 9.3.4.5 USB-PD BMC Receiver
        6. 9.3.4.6 Squelch Receiver
      5. 9.3.5  VCONN
      6. 9.3.6  Cable Plug and Orientation Detection
        1. 9.3.6.1 Configured as a Source
        2. 9.3.6.2 Configured as a Sink
        3. 9.3.6.3 Overvoltage Protection (Px_CC1, Px_CC2)
      7. 9.3.7  ADC
        1. 9.3.7.1 ADC Divider Ratios
      8. 9.3.8  BC 1.2, Legacy and Fast Charging Modes (Px_DP, Px_DM)
      9. 9.3.9  USB2.0 Low-Speed Endpoint
      10. 9.3.10 Digital Interfaces
        1. 9.3.10.1 General GPIO
        2. 9.3.10.2 I2C Buffer
      11. 9.3.11 I2C Interface
        1. 9.3.11.1 I2C Interface Description
        2. 9.3.11.2 I2C Clock Stretching
        3. 9.3.11.3 I2C Address Setting
        4. 9.3.11.4 Unique Address Interface
        5. 9.3.11.5 I2C Pullup Resistor Calculation
      12. 9.3.12 Digital Core
        1. 9.3.12.1 Device Memory
        2. 9.3.12.2 Core Microprocessor
      13. 9.3.13 NTC Input
      14. 9.3.14 Thermal Sensors and Thermal Shutdown
    4. 9.4 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Application GUI Selections
        2. 10.2.2.2 EEPROM Selection
        3. 10.2.2.3 EN/UVLO
        4. 10.2.2.4 Sense Resistor, RSNS, RCSP, RCSN and CFILT
        5. 10.2.2.5 Inductor Currents
        6. 10.2.2.6 Output Capacitor
        7. 10.2.2.7 Input Capacitor
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.3.2 Switching Frequency, Frequency Dither, Phase-Shift and Synchronization

The PWM oscillator frequency (fsw) is programmed by firmware using the application configuration GUI. The switching converter is intended for operation below the AM radio band (520 kHz - 1730 kHz). Three nominal fsw settings below are available: 300 kHz, 400 kHz and 450 kHz.

Frequency dithering can be enabled by firmware via the application GUI. When enabled, the nominal oscillator frequency is dithered by ±FSSS (approximately ±10%) using triangular waveform modulation (see Dithering using triangular waveform modulation). The dither period τM is the reciprocal of the dither modulation frequency FSSS_MOD. Two firmware selectable dither modulation frequencies FSSS_M are available: 10 and 25 kHz. Dithering spreads the spectral peaks generated by switching, thereby reducing the peak harmonic levels and easing EMI filter design.

GUID-0AA95BCD-F6ED-47B9-AF06-2659DEA330F8-low.gifFigure 9-13 Dithering Using Triangular Waveform Modulation

Multiple converters can be synchronized using the SYNC pin. This pin can be firmware-configured as either an output SYNC(o) or an input SYNC(i).

  • SYNC(o): The switching clock is placed on the SYNC(o) pin. This waveform will have a duty cycle of approximately 50%. If frequency dithering is configured by firmware, this signal will also exhibit dithering. Four phase settings are available by firmware configuration to shift the SYNC(o) output relative to the internal switching clock by 0°, 90°, 120°, or 180°. SYNC(o) is used to slave other DC/DC converter clocks to the switching converter clock inside the TPS25772-Q1. When two dc/dc converters operate out of phase, peak input current from the battery is reduced and total input bulk capacitance requirements decrease.
    GUID-20221025-SS0I-MC1B-VKNJ-BQXXGC8MQ1NR-low.svg Figure 9-14 SYNC(o) Phase Shift
    GUID-684BC646-54C3-4D30-8E6D-9C46BD655B92-low.gif Figure 9-15 Using SYNC(o) to slave DC/DC Converter
  • SYNC(i): The internal clock is synchronized to the pulse train on the SYNC(i) pin. This feature is used to slave the TPS25772-Q1 to an external clock. The period of this clock must meet synchronization requirements in SYNC(i) frequency ranges or the TPS25772-Q1 will instead use its internal switching clock. If an external clock deviates outside of the acceptable frequency range and then returns to within the acceptable frequency range, the TPS25772-Q1 will resume operation from the external clock after counting 8 consecutive clocks meeting the criteria of Table 9-6. When SYNC(i) is configured, frequency dithering is disabled when operating from the internal clock following a failure of the external clock.

Table 9-6 SYNC(i) Frequency Ranges
fSW Firmware SettingAllowed SYNC(i) Frequency Range
MINMAX
300 kHz250 kHz353 kHz
400 kHz334 kHz470 kHz
450 kHz376 kHz530 kHz