JAJSN99A December   2022  – September 2023 TPS25772-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Recommended Components
    5. 7.5  Thermal Information
    6. 7.6  Buck-Boost Regulator
    7. 7.7  CC Cable Detection Parameters
    8. 7.8  CC VCONN Parameters
    9. 7.9  CC PHY Parameters
    10. 7.10 Thermal Shutdown Characteristics
    11. 7.11 Oscillator Characteristics
    12. 7.12 ADC Characteristics
    13. 7.13 TVS Parameters
    14. 7.14 Input/Output (I/O) Characteristics
    15. 7.15 BC1.2 Characteristics
    16. 7.16 I2C Requirements and Characteristics
    17. 7.17 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Device Power Management and Supervisory Circuitry
        1. 9.3.1.1 VIN UVLO and Enable/UVLO
        2. 9.3.1.2 Internal LDO Regulators
      2. 9.3.2  TVSP Device Configuration and ESD Protection
      3. 9.3.3  Buck-Boost Regulator
        1. 9.3.3.1  Buck-Boost Regulator Operation
        2. 9.3.3.2  Switching Frequency, Frequency Dither, Phase-Shift and Synchronization
        3. 9.3.3.3  VIN Supply and VIN Over-Voltage Protection
        4. 9.3.3.4  Feedback Paths and Error Amplifiers
        5. 9.3.3.5  Transconductors and Compensation
        6. 9.3.3.6  Output Voltage DAC, Soft-Start and Cable Droop Compensation
        7. 9.3.3.7  VBUS Overvoltage Protection
        8. 9.3.3.8  VBUS Undervoltage Protection
        9. 9.3.3.9  Current Sense Resistor (RSNS) and Current Limit Operation
        10. 9.3.3.10 Buck-Boost Peak Current Limits
      4. 9.3.4  USB-PD Physical Layer
        1. 9.3.4.1 USB-PD Encoding and Signaling
        2. 9.3.4.2 USB-PD Bi-Phase Marked Coding
        3. 9.3.4.3 USB-PD Transmit (TX) and Receive (Rx) Masks
        4. 9.3.4.4 USB-PD BMC Transmitter
        5. 9.3.4.5 USB-PD BMC Receiver
        6. 9.3.4.6 Squelch Receiver
      5. 9.3.5  VCONN
      6. 9.3.6  Cable Plug and Orientation Detection
        1. 9.3.6.1 Configured as a Source
        2. 9.3.6.2 Configured as a Sink
        3. 9.3.6.3 Overvoltage Protection (Px_CC1, Px_CC2)
      7. 9.3.7  ADC
        1. 9.3.7.1 ADC Divider Ratios
      8. 9.3.8  BC 1.2, Legacy and Fast Charging Modes (Px_DP, Px_DM)
      9. 9.3.9  USB2.0 Low-Speed Endpoint
      10. 9.3.10 Digital Interfaces
        1. 9.3.10.1 General GPIO
        2. 9.3.10.2 I2C Buffer
      11. 9.3.11 I2C Interface
        1. 9.3.11.1 I2C Interface Description
        2. 9.3.11.2 I2C Clock Stretching
        3. 9.3.11.3 I2C Address Setting
        4. 9.3.11.4 Unique Address Interface
        5. 9.3.11.5 I2C Pullup Resistor Calculation
      12. 9.3.12 Digital Core
        1. 9.3.12.1 Device Memory
        2. 9.3.12.2 Core Microprocessor
      13. 9.3.13 NTC Input
      14. 9.3.14 Thermal Sensors and Thermal Shutdown
    4. 9.4 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Application GUI Selections
        2. 10.2.2.2 EEPROM Selection
        3. 10.2.2.3 EN/UVLO
        4. 10.2.2.4 Sense Resistor, RSNS, RCSP, RCSN and CFILT
        5. 10.2.2.5 Inductor Currents
        6. 10.2.2.6 Output Capacitor
        7. 10.2.2.7 Input Capacitor
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range of -40°C to 150°C and AGND = PGND (unless otherwise noted)(1)(2)
MIN MAX UNIT
Input voltage range IN (3)(4) to PGND –0.3 40 V
Input voltage range IN with respect to SW1 –0.3 25 V
Input voltage range EN/UVLO (5) to AGND –0.3 internally limited V
Input voltage range BOOT1 with respect to SW1 –0.3 6 V
Input voltage range BOOT2 with respect to SW2 (6) –0.3 6 V
Input voltage range SW1 (7) to PGND –0.3 24 V
Input voltage range SW2 (8) to PGND –0.3 24 V
Input voltage range SW2 to OUT 17.5 V
Input voltage range CSP to PGND –0.3 24 V
Input voltage range CSN/BUS to PGND –0.3 24 V
Input voltage range CSP to CSN -0.3 0.3 V
Input voltage range AGND to PGND –0.3 0.3 V
Output voltage range OUT to PGND –0.3 24 V
Output voltage range LDO_5V to PGND –0.3 6 V
Output voltage range LDO_3V3 to AGND –0.3 6 V
Output voltage range LDO_1V5 to AGND –0.3 2 V
I/O voltage range TVSP to PGND –0.3 30 V
I/O voltage range I2C_SCL1 to AGND –0.3 6 V
I/O voltage range I2C_SDA1 to AGND –0.3 6 V
I/O voltage range GPIO9, IRQ1 to AGND –0.3 6 V
I/O voltage range PA_CC1 to AGND –0.3 30 V
I/O voltage range PA_CC2 to AGND –0.3 30 V
I/O voltage range PA_DM to AGND –0.3 30 V
I/O voltage range GPIO7 to AGND –0.3 6 V
I/O voltage range PA_DP to AGND –0.3 30 V
I/O voltage range GPIO8 to AGND –0.3 6 V
I/O voltage range PB_CC1 to AGND –0.3 30 V
I/O voltage range GPIO0  to AGND –0.3 6 V
I/O voltage range PB_CC2 to AGND –0.3 30 V
I/O voltage range GPIO1, IRQ2 to AGND –0.3 6 V
I/O voltage range PB_DP to AGND –0.3 30 V
I/O voltage range GPIO2, I2C_SCL2 to AGND –0.3 6 V
I/O voltage range PB_DM to AGND –0.3 30 V
I/O voltage range GPIO3, I2C_SDA2 to AGND –0.3 6 V
I/O voltage range PB_BUS to AGND –0.3 30 V
I/O voltage range GPIO4 –0.3 6 V
I/O voltage range GPIO5, NTC to AGND –0.3 6 V
I/O voltage range GPIO6, SYNC to AGND –0.3 6 V
Input current EN/UVLO 0 2 mA
Output current Positive source current on PA_CC1, PA_CC2, PB_CC1, PB_CC2 internally limited A
Output current GPIO 2, 3, 5, 6, 7, 8  0.0010 A
Output current GPIO 0, 1, 4, 9 0.005 A
Output current positive sink current for I2C_SDA1, I2C_SCL1, I2C_SDA2, I2C2_SCL2 internally limited A
Output current positive source current for LDO_5V, LDO_3V3, LDO_1V5 internally limited A
TA Operating ambient temperature –40 125 °C
TJ Operating junction temperature –40 150 °C
TSTG Storage temperature –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to PGND or AGND. Connect the PGND pin directly to the Ground plane of the board. The PGND and AGND traces can be connected near the AGND pin.
(3) When the buck-boost is operating and VIN exceeds 18 V, the positive slew rate dVIN/dt must not exceed 200V/ms.
(4) When applying VIN, the time from VIN exceeding 5 V to VIN exceeding 25 V must not be less than 2 µs. This is normally achieved by properly sizing the input EMI filter.
(5) EN/UVLO pin is internally clamped to 10V. Ensure input current rating is not exceeded by connecting current limit resistor.
(6) BOOT2 with respect to SW2 during OUT overvoltage conditions can be -15 V due to internal clamp.
(7) SW1 can undershoot PGND by -1 V during negative switching transients as up to 10A (peak) may flow through the body diode. Typical duration ~20 ns. SW1 can overshoot OUT by 1 V during positive transients. Typical duration ~ 20 ns.
(8) SW2 can undershoot PGND by -2 V during switching transients as up to 10A (peak) may flow through the body diode. Typical duration ~20 ns. SW2 can overshoot OUT by 1 V during positive transients. Typical duration ~20 ns.