When the load draws current during the turn-on sequence, there is additional power dissipated. Considering a resistive load during start-up R_L(SU), load current ramps up proportionally with increase in output voltage during T_dVdt time. Equation 19 shows the average power dissipation in the internal FET during charging time due to resistive load.

Equation 19.

Equation 20 gives the total power dissipated in the device during start-up.

Equation 20.

The power dissipation, with and without load, for selected start-up time must not exceed the start-up thermal shutdown limits as shown in Thermal Shutdown Plot During Start-up.

Figure 9-2 Thermal Shutdown Plot During Start-up

For the design example under discussion, the output voltage has to be ramped up in 20 ms, which mandates a slew-rate of 0.6 V/ms for a 12-V rail.

The required C_dVdt capacitance on dVdt pin to set 0.6-V/ms slew rate can be calculated using Equation 21.

Equation 21.

The dVdt capacitor is subjected to typically V_IN + 4 V during startup. The high voltage bias leads to a drop in the effective capacitor value. So, it is suggested to choose 20% higher than the calculated value, which gives 9.2 nF. Choose closest 10% standard value: 10 nF

The 10 nF C_dVdt capacitance sets a slew-rate of 0.46 V/ms and output ramp time T_dVdt of 26 ms.

The inrush current drawn by the load capacitance C_OUT during ramp-up can be calculated using Equation 22.

Equation 22.

The inrush power dissipation can be calculated using Equation 23.

Equation 23.

For 3.9 W of power loss, the thermal shutdown time of the device must be greater than the ramp-up time T_dVdt to ensure a successful start-up. Figure 9-2 shows the start-up thermal shutdown limit. For 3.9 W of power, the shutdown time is approximately 100 ms. So it is safe to use 26 ms as the start-up time without any load on the output.

The additional power dissipation when a 10-Ω load is present during start-up is calculated using Equation 24.

Equation 24.

The total device power dissipation during start-up can be calculated using Equation 25.

Equation 25.

From Thermal Shutdown Plot During Start-up, the thermal shutdown time for 6.3 W is approximately 40 ms. It is safe to have 30% margin to allow for variation of system parameters such as load, component tolerance, and input voltage. So it is well within acceptable limits to use the 10 nF for C_dVdt capacitor with start-up load of 10 Ω.

When C_OUT is large, there is a need to decrease the power dissipation during start-up. This can be done by increasing the value of the C_dVdt capacitor. A spreadsheet tool TPS25983xx Design Calculator available on the web can be used for iterative calculations.