JAJSGC0F September   2009  – October 2018 TPS386000 , TPS386040

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      TPS386000代表的アプリケーション回路： FPGA電源の監視
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Voltage Monitoring
      2. 8.3.2 Manual Reset
      3. 8.3.3 Watchdog Timer
      4. 8.3.4 Reset Output
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Undervoltage Detection
      2. 9.1.2 Undervoltage and Overvoltage Detection
      3. 9.1.3 Sensing a Negative Voltage
      4. 9.1.4 Reset Delay Time
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
        1. 12.1.1.1 評価モジュール
        2. 12.1.1.2 SPICEモデル
      2. 12.1.2 デバイスの項目表記
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 関連リンク
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

Over the operating temperature range of TJ = –40°C to 125°C, 1.8 V < VDD < 6.5 V, RRESETn (n = 1, 2, 3, 4) = 100 kΩ to VDD (TPS386000 only), CRESETn (n = 1, 2, 3, 4L, 4H) = 50 pF to GND, RWDO = 100 kΩ to VDD, CWDO = 50 pF to GND, VMR = 100 kΩ to VDD, WDI = GND, and CTn (n = 1, 2, 3, 4) = open, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD Input supply range 1.8 6.5 V
IDD Supply current (current into VDD pin) VDD = 3.3 V, RESETn or RESETn not asserted, WDI toggling(1), no output load, and VREF open 11 19 μA
VDD = 6.5 V, RESETn or RESETn not asserted, WDI toggling(1), no output load, and VREF open 13 22
Power-up reset voltage(2)(3) VOL (max) = 0.2 V, IRESETn = 15 μA 0.9 V
VITN Negative-going input threshold voltage SENSE1, SENSE2, SENSE3, SENSE4L 396 400 404 mV
VITP Positive-going input threshold voltage SENSE4H 396 400 404 mV
VHYSN Hysteresis (positive-going) on VITN SENSE1, SENSE2, SENSE3, SENSE4L 3.5 10 mV
VHYSP Hysteresis (negative-going) on VITP SENSE4H 3.5 10 mV
ISENSE Input current at SENSEm pin VSENSEm = 0.42 V –25 ±1 +25 nA
ICT CTn pin charging current CT1 CCT1 > 220 pF, VCT1 = 0.5 V(4) 245 300 355 nA
CT2, CT3, CT4 CCTn > 220 pF, VCTn = 0.5 V(4) 235 300 365
VTH(CTn) CTn pin threshold CCTn > 220 pF 1.18 1.238 1.299 V
VIL MR and WDI logic low input 0 0.3VDD V
VIH MR and WDI logic high input 0.7VDD V
VOL Low-level RESETn or RESETn output voltage IOL = 1 mA 0.4 V
SENSEn = 0 V, 1.3 V < VDD < 1.8 V,
IOL = 0.4 mA(2) 		0.3 V
Low-level WDO output voltage IOL = 1 mA 0.4
VOH High-level RESETn or RESETn output voltage TPS386040 only IOL = –1 mA VDD – 0.4 V
High-level WDO output voltage TPS386040 only IOL = –1 mA VDD – 0.4 V
SENSEn = 0 V, 1.3 V < VDD < 1.8 V,
IOL = –0.4 mA(2) 		VDD – 0.3
ILKG RESETn, RESETn, WDO, and WDO leakage current TPS386000 only VRESETn = 6.5 V, RESETn, RESETn, WDO, and WDO are logic high –300 300 nA
VREF Reference voltage output 1 μA < IVREF < 0.2 mA (source only, no sink) 1.18 1.2 1.22 V
CIN Input pin capacitance CTn: 0 V to VDD, other pins: 0 V to 6.5 V 5 pF
(1) Toggling WDI for a period less than tWDT negatively affects IDD.
(2) These specifications are beyond the recommended VDD range, and only define RESETn or RESETn output performance during VDD ramp up.
(3) The lowest supply voltage (VDD) at which RESETn or RESETn becomes active; tRISE(VDD) ≥ 15 μs/V.
(4) CTn (where n = 1, 2, 3, or 4) are constant current charging sources working from a range of 0 V to VTH(CTn), and the device is tested at VCTn = 0.5 V. For ICT performance between 0 V and VTH(CTn), see Figure 28.