JAJSGC0F September 2009 – October 2018 TPS386000 , TPS386040
PRODUCTION DATA.
The TPS3860x0 provides a watchdog timer with a dedicated watchdog error output, WDO or WDO. The WDO or WDO output enables application board designers to easily detect and resolve the hang-up status of a processor. As with MR, the watchdog timer function of the device is also tied to SVS-1. Figure 5 shows the timing diagram of the WDT function. Once RESET1 or RESET1 is released, the internal watchdog timer starts its countdown. Inputting a logic level transition at WDI resets the internal timer count and the timer restarts the countdown. If the TPS3860x0 fails to receive any WDI rising or falling edge within the WDT period, the WDT times out and asserts WDO or WDO. After WDO or WDO is asserted, the device holds the status with the internal latch circuit. To clear this time-out status, a reset assertion of RESET1 or RESET is required. That is, a negative pulse to MR, a SENSE1 voltage less than VITN, or a VDD power down is required.
To reset the processor by WDT time-out, WDO can be combined with RESET1 by using the wired-OR with the TPS386000 option.
For legacy applications where the watchdog timer time-out causes RESET1 to assert, connect WDO to MR; see Figure 35 for the connections and see Figure 6 and Figure 7 for the timing diagrams.