JAJSGC0F September   2009  – October 2018 TPS386000 , TPS386040

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      TPS386000代表的アプリケーション回路: FPGA電源の監視
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Voltage Monitoring
      2. 8.3.2 Manual Reset
      3. 8.3.3 Watchdog Timer
      4. 8.3.4 Reset Output
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Undervoltage Detection
      2. 9.1.2 Undervoltage and Overvoltage Detection
      3. 9.1.3 Sensing a Negative Voltage
      4. 9.1.4 Reset Delay Time
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
        1. 12.1.1.1 評価モジュール
        2. 12.1.1.2 SPICEモデル
      2. 12.1.2 デバイスの項目表記
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 関連リンク
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Overview

The TPS3860x0 multi-channel supervisory family of devices combines four complete SVS function sets into one IC, along with a watchdog timer, a window comparator, and negative voltage sensing. The design of each SVS channel is based on the single-channel supervisory device series, TPS3808. The TPS3860x0 is designed to assert RESETn or RESETn signals, as shown in Table 1, Table 2, Table 3, and Table 4. The RESETn or RESETn outputs remain asserted during a user-configurable delay time after the event of reset release (see the Reset Delay Timesection).

The TPS3860x0 has a very low quiescent current of 11 μA (typical) and is available in a small, 4-mm × 4-mm, 20-Pin VQFN package.