JAJSGE0C JANUARY   2014  – October 2018 TPS40425

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1. 3.1 アプリケーション概略図 （デュアル出力）
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Asynchronous Pulse Injection (API)
      2. 7.3.2  Adaptive Voltage Scaling (AVS)
      3. 7.3.3  Switching Frequency and Synchronization
      4. 7.3.4  Voltage Reference
      5. 7.3.5  Output Voltage and Remote Sensing Amplifier
      6. 7.3.6  Current Sensing and Temperature Sensing Modes
        1. 7.3.6.1 Non Smart-Power Operation
        2. 7.3.6.2 Smart-Power Operation.
      7. 7.3.7  Current Sensing
      8. 7.3.8  Temperature Sensing
      9. 7.3.9  Current Sharing
      10. 7.3.10 Linear Regulators
      11. 7.3.11 Power Sequence Between TPS40425 Device and Power Stage
      12. 7.3.12 PWM Signal
        1. 7.3.12.1 PWM Behavior During Soft-start Operation
      13. 7.3.13 Startup and Shutdown
      14. 7.3.14 Pre-Biased Output Start-up
      15. 7.3.15 PGOOD Indication
      16. 7.3.16 Overcurrent Protection
      17. 7.3.17 Overvoltage/Undervoltage Protection
      18. 7.3.18 Overtemperature Fault Protection
      19. 7.3.19 Input Undervoltage Lockout (UVLO)
      20. 7.3.20 Fault Communication
      21. 7.3.21 Fault Protection Summary
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Multi-Phase Applications
    6. 7.6 Register Maps
      1. 7.6.1 PMBus General Description
      2. 7.6.2 PMBus Functionality
        1. 7.6.2.1 PMBus Address
        2. 7.6.2.2 PMBus Connections
        3. 7.6.2.3 PMBus Data Format
        4. 7.6.2.4 PMBus Output Voltage Adjustment
          1. 7.6.2.4.1 No Margin Voltage
          2. 7.6.2.4.2 Margin High Voltage State
          3. 7.6.2.4.3 Margin Low State
      3. 7.6.3 Reading the Output Current
      4. 7.6.4 Soft-Start Time
      5. 7.6.5 Turn-On/Turn-Off Delay and Sequencing
    7. 7.7 Supported PMBus Commands
      1. 7.7.1  PAGE (00h)
      2. 7.7.2  OPERATION (01h)
      3. 7.7.3  ON_OFF_CONFIG (02h)
      4. 7.7.4  CLEAR_FAULTS (03h)
      5. 7.7.5  WRITE_PROTECT (10h)
      6. 7.7.6  STORE_USER_ALL (15h)
      7. 7.7.7  RESTORE_USER_ALL (16h)
      8. 7.7.8  CAPABILITY (19h)
      9. 7.7.9  VOUT_MODE (20h)
      10. 7.7.10 VIN_ON (35h)
      11. 7.7.11 VIN_OFF (36h)
      12. 7.7.12 IOUT_CAL_GAIN (38h)
      13. 7.7.13 IOUT_CAL_OFFSET (39h)
      14. 7.7.14 IOUT_OC_FAULT_LIMIT (46h)
      15. 7.7.15 IOUT_OC_FAULT_RESPONSE (47h)
      16. 7.7.16 IOUT_OC_WARN_LIMIT (4Ah)
      17. 7.7.17 OT_FAULT_LIMIT (4Fh)
      18. 7.7.18 OT_WARN_LIMIT (51h)
      19. 7.7.19 TON_RISE (61h)
      20. 7.7.20 STATUS_BYTE (78h)
      21. 7.7.21 STATUS_WORD (79h)
      22. 7.7.22 STATUS_VOUT (7Ah)
      23. 7.7.23 STATUS_IOUT (7Bh)
      24. 7.7.24 STATUS_TEMPERATURE (7Dh)
      25. 7.7.25 STATUS_CML (7Eh)
      26. 7.7.26 STATUS_MFR_SPECIFIC (80h)
      27. 7.7.27 READ_VOUT (8Bh)
      28. 7.7.28 READ_IOUT (8Ch)
      29. 7.7.29 READ_TEMPERATURE_2 (8Eh)
      30. 7.7.30 PMBus_REVISION (98h)
      31. 7.7.31 MFR_SPECIFIC_00 (D0h)
      32. 7.7.32 MFR_SPECIFIC_04 (VREF_TRIM) (D4h)
      33. 7.7.33 MFR_SPECIFIC_05 (STEP_VREF_MARGIN_HIGH) (D5h)
      34. 7.7.34 MFR_SPECIFIC_06 (STEP_VREF_MARGIN_LOW) (D6h)
      35. 7.7.35 MFR_SPECIFIC_07 (PCT_VOUT_FAULT_PG_LIMIT) (D7h)
      36. 7.7.36 MFR_SPECIFIC_08 (SEQUENCE_TON_TOFF_DELAY) (D8h)
      37. 7.7.37 MFR_SPECIFIC_16 (COMM_EEPROM_SPARE) (E0h)
      38. 7.7.38 MFR_SPECIFIC_21 (OPTIONS) (E5h)
      39. 7.7.39 MFR_SPECIFIC_22 (PWM_OSC_SELECT) (E6h)
      40. 7.7.40 MFR_SPECIFIC_23 (MASK SMBALERT) (E7h)
      41. 7.7.41 MFR_SPECIFIC_25 (AVS_CONFIG) (E9h)
      42. 7.7.42 MFR_SPECIFIC_26 (AVS_ADDRESS) (EAh)
      43. 7.7.43 MFR_SPECIFIC_27 (AVS_DAC_DEFAULT) (EBh)
      44. 7.7.44 MFR_SPECIFIC_28 (AVS_CLAMP_HI) (ECh)
      45. 7.7.45 MFR_SPECIFIC_29 (AVS_CLAMP_LO) (EDh)
      46. 7.7.46 MFR_SPECIFIC_30 (TEMP_OFFSET) (EEh)
      47. 7.7.47 MFR_SPECIFIC_32 (API_OPTIONS) (F0h)
      48. 7.7.48 MFR_SPECIFIC_44 (DEVICE_CODE) (FCh)
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Dual-Output Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Design Procedure
        1. 8.2.3.1  Switching Frequency Selection
        2. 8.2.3.2  Inductor Selection
        3. 8.2.3.3  Output Capacitor Selection
          1. 8.2.3.3.1 Output Voltage Deviation During Load Transient
          2. 8.2.3.3.2 Output Voltage Ripple
        4. 8.2.3.4  Input Capacitor Selection
        5. 8.2.3.5  VDD, BP5, BP3 Bypass Capacitor
        6. 8.2.3.6  R-C Snubber
        7. 8.2.3.7  Current and Temperature Sensor
        8. 8.2.3.8  Power Sequence Between the TPS40425 Device and Power Stage
        9. 8.2.3.9  Output Voltage Setting and Frequency Compensation Selection
        10. 8.2.3.10 Key PMBus Parameter Selection
          1. 8.2.3.10.1 MFR_SPECIFIC_21 (OPTIONS)
            1. 8.2.3.10.1.1 IOUT_CAL_GAIN
            2. 8.2.3.10.1.2 Enable and UVLO
            3. 8.2.3.10.1.3 Soft-Start Time
            4. 8.2.3.10.1.4 Overcurrent Threshold and Response
      4. 8.2.4 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Layout Guidelines for TPS40425 Device
      2. 10.1.2 Layout Guidelines for Power Stage Device
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 Texas Instruments Fusion Digital Power Designer
        2. 11.1.1.2 TPS40kループ補償ツール
    2. 11.2 商標
    3. 11.3 静電気放電に関する注意事項
    4. 11.4 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.7.25 STATUS_CML (7Eh)

Format Unsigned binary
Description The STATUS_ CML command returns one byte containing PMBus serial communication faults.
Default 00000000 (binary)
read only
7 6 5 4 3 2 1 0
ivc ivd pec mem 0 0 oth 0
Bits Field Name Description
7 ivc ( = Invalid/Unsupported Command in the PMBus Specification)

(Format: binary)

Invalid or unsupported Command Received

0: (Default) Invalid or unsupported Command not Received.

1: Invalid or unsupported Command Received.

An attempt to write an invalid PAGE 1 SLAVE channel command results in a NACK’d command and the reporting of an IVC fault and triggering of SMB_ALERT.
6 ivd ( = Invalid/Unsupported Data in the PMBus Specification)

(Format: binary)

Invalid or unsupported data Received

0: (Default) Invalid or unsupported data not Received.

1: Invalid or unsupported data Received.
5 pec ( = Packet Error Check Failed in the PMBus Specification)

(Format: binary)

Packet Error Check Failed

This is a CRC byte sent at the end of each data packet. It is implemented as CRC(x) = x8 + x2 + x1 + 1

0: (Default) Packet Error Check Passed

1: Packet Error Check Failed
4 mem ( = Memory Fault Detected in the PMBus Specification)

(Format: binary)

Memory Fault Detected

This bit indicates a fault with the internal memory.

0: (Default) No fault detected

1: Fault detected
3:2 0 Default: 0
1 oth ( = Other Communication Fault in the PMBus Specification)

(Format: binary)

Other Communication Fault

0: (Default) A communication fault other than the ones listed in this table has not occurred.

1: A communication fault other than the ones listed in this table has occurred.
0 0 Default: 0