There are several industry techniques used to compensate DC/DC regulators. The method presented here is easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between 60 and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to the TPS54020. Because the slope compensation is ignored, the actual cross over frequency is usually lower than the cross over frequency used in the calculations. Use the PSPICE model for a more accurate design.

First, the modulator pole, f_P(mod), and the esr zero, f_Z(mod), must be calculated using Equation 30 and Equation 31.

For the output capacitance, use a derated value of 225 μF. As a quick estimate, an f_C value between three and five times the double pole frequency of the output filter is chosen. In this case, an f_C of 35 kHz was selected. f_P(mod) is 3.93 kHz and f_Z(mod) is 10.6 MHz.

Equation 30.

Equation 31.

Now the compensation components can be calculated. First, calculate the value for C12 which sets the gain of the compensated network at low frequencies far below f_C. Because the desired f_C is 35 kHz, and the expected gain curve is a single pole roll off, two decades below f_C (which is 350 Hz), the gain should be +40 dB. Following this logic, the plant gain at DC is calculated in Equation 32.

Equation 32.

This implies that at 350 Hz, the compensation pole capacitor C12 should reduce the gain by (80.94-40) =
40.94 dB, or result in a gain of -40.94 dB. (See Equation 33)

Equation 33.

Equation 34.

Equation 35.

where

• f_SW is in kHz

The closest standard value is 22 nF.

From Equation 30, the required compensation zero resulting from R13 should be placed at f_P(mod) of 3.93 kHz.

Equation 36.

Equation 37.

where

• f_Z(comp) is in kHz
• C12 is in nF
• R13 is in kΩ

This value was adjusted after actual Bode measurements to 3.01 kΩ.

An additional high frequency pole can be used if necessary by adding a capacitor in parallel with the series combination of R13 and C12. The pole frequency can be placed at the ESR zero frequency of the output capacitor as given by Equation 13. Use Equation 38 to calculate the required capacitor value for C10.

Equation 38.

This value was adjusted upwards to 22 0pF to reduce jitter.