Figure 9-2 is a small signal model that can be used to understand how to design the frequency compensation network. This is a simplified model that does not include the effects of slope compensation. The device power stage, or Plant, can be approximated by a voltage controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer function is shown in Equation 10 and consists of a dc gain, one dominant pole and one ESR zero. The quotient of the change in switch current and the change in COMP pin voltage (node c in Figure 9-1) is the power stage transconductance (gm_ps) which is 20 A/V for the TPS54020 (when ILIM is open). The DC gain or amplification of the power stage, A_DC, is the product of gm_ps and the load resistance RL as shown in Equation 11 with resistive loads. As the load current increases, the DC gain decreases. This variation with load may seem problematic at first glance, but fortunately the dominant pole moves with load current (see Equation 12). The combined effect is highlighted by the dashed line in Figure 9-3. As the load current decreases, the gain increases and the pole frequency reduces, keeping the 0-dB crossover frequency the same for the varying load conditions which makes it easier to design the frequency compensation.

Figure 9-2 Simplified Small Signal Model for Peak Current Mode Control

Figure 9-3 Simplified Frequency Response for Peak Current Mode Control

The simplified control-to-output transfer function is shown in Equation 10.

Equation 10.

The power stage DC gain is shown in Equation 11.

Equation 11.

The pole from load is show in Equation 12.

Equation 12.

To calculate the zero from the capacitor ESR use Equation 13.

Equation 13.

where

• g_M(ea) is the transconductance amplifier gain (1300 μA/V)
• g_M(ps) is the power stage gain (20 A/V)
• R_LOAD is the load resistance
• C_OUT is the output capacitance
• R_ESR is the equivalent series resistance of the output capacitor