JAJSOW5F April   2006  – January 2024 TPS5420

PRODUCTION DATA  

  1.   1
  2. 1特長
  3. 2アプリケーション
  4. 3概要
  5. 4静電気放電に関する注意事項
  6. 5Ordering Information
  7. 6Pin Assignments
    1. 6.1 Terminal Functions
  8. 7Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information 
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8Application Information
    1. 8.1 Functional Block Diagram
    2. 8.2 Detailed Description
      1. 8.2.1  Oscillator Frequency
      2. 8.2.2  Voltage Reference
      3. 8.2.3  Enable (ENA) and Internal Slow Start
      4. 8.2.4  Undervoltage Lockout (UVLO)
      5. 8.2.5  Boost Capacitor (BOOT)
      6. 8.2.6  Output Feedback (VSENSE)
      7. 8.2.7  Internal Compensation
      8. 8.2.8  Voltage Feed Forward
      9. 8.2.9  Pulse-Width-Modulation (PWM) Control
      10. 8.2.10 Overcurrent Limiting
      11. 8.2.11 Overvoltage Protection
      12. 8.2.12 Thermal Shutdown
      13. 8.2.13 PCB Layout
      14. 8.2.14 Application Circuits
      15. 8.2.15 Design Procedure
        1. 8.2.15.1  Design Parameters
        2. 8.2.15.2  Switching Frequency
        3. 8.2.15.3  Input Capacitors
        4. 8.2.15.4  Output Filter Components
          1. 8.2.15.4.1 Inductor Selection
          2. 8.2.15.4.2 Capacitor Selection
          3.        40
          4.        41
        5. 8.2.15.5  Output Voltage Setpoint
        6. 8.2.15.6  Boot Capacitor
        7. 8.2.15.7  Catch Diode
        8. 8.2.15.8  Additional Circuits
        9. 8.2.15.9  Circuit Using Ceramic Output Filter Capacitors
        10. 8.2.15.10 Output Filter Component Selection
        11. 8.2.15.11 External Compensation Network
    3. 8.3 Advanced Information
      1. 8.3.1 Output Voltage Limitations
      2. 8.3.2 Internal Compensation Network
      3. 8.3.3 Thermal Calculations
    4. 8.4 Performance Graphs
  10. 9Revision History

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Performance Graphs

The performance graphs in Figure 8-6 - Figure 8-12 are applicable to the circuit in Figure 8-3. TA = 25°C. unless otherwise specified.

GUID-790A1B61-CB35-4868-9977-476FD931C8A4-low.gifFigure 8-6 Efficiency vs. Output Current
GUID-5AB22A4F-6D61-4F5A-B6EB-C2AE1C9FB605-low.gifFigure 8-8 Input Regulation % vs. Input Voltage
GUID-8483BC17-0690-4108-ADCC-DE1E9CD65960-low.gifFigure 8-10 Output Voltage Ripple and PH Node, IO = 3 A
GUID-14C6CA54-5D09-4E9B-AFDE-1AC3BA79DC7B-low.gifFigure 8-12 Startup Waveform, VIN and VOUT
GUID-4310692C-152A-46B4-830C-7936E3E347FD-low.gifFigure 8-7 Output Regulation % vs. Output Current
GUID-06C59053-347C-4F10-B0A9-29D53C4E4132-low.gifFigure 8-9 Input Voltage Ripple and PH Node, IO = 3 A
GUID-A7F3871C-7A8A-43A9-AAFD-12EBF1E3793D-low.gifFigure 8-11 Transient Response, Io Step 0.5 to 1.5 A
GUID-C2B2A6B3-BEA6-49E4-899D-3E3BAC567EB6-low.gifFigure 8-13 Startup Waveform, ENA and VOUT