Due to the internal design of the TPS5420, there are both upper and lower output voltage limits for any given input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 87% and is given by:

Equation 21.

Where:

V_INMIN = minimum input voltage

I_OMAX = maximum load current

V_D = catch diode forward voltage.

R_L= output inductor series resistance.

This equation assumes maximum on resistance for the internal high side FET.

The lower limit is constrained by the minimum controllable on time which may be as high as 200 ns. The approximate minimum output voltage for a given input voltage and minimum load current is given by:

Equation 22.

Where:

V_INMAX = maximum input voltage

I_OMIN = minimum load current

V_D = catch diode forward voltage.

R_L= output inductor series resistance.

This equation assumes nominal on resistance for the high side FET and accounts for worst case variation of operating frequency set point. Any design operating near the operational limits of the device should be checked to assure proper functionality.