JAJSGT4C June   2014  – September 2021 TPS55340-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operation
      2. 7.3.2 Switching Frequency
      3. 7.3.3 Overcurrent Protection and Frequency Foldback
        1. 7.3.3.1 Minimum On Time and Pulse Skipping
      4. 7.3.4 Voltage Reference and Setting Output Voltage
      5. 7.3.5 Soft Start
      6. 7.3.6 Slope Compensation
      7. 7.3.7 Enable and Thermal Shutdown
      8. 7.3.8 Undervoltage Lockout (UVLO)
      9. 7.3.9 Thermal Considerations
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With VI < 2.9 V (Minimum VI)
      2. 7.4.2 Operation With EN Control
      3. 7.4.3 Operation at Light Loads
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 TPS55340-Q1 Boost Converter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2  Selecting the Switching Frequency (R4)
          3. 8.2.1.2.3  Determining the Duty Cycle
          4. 8.2.1.2.4  Selecting the Inductor (L1)
          5. 8.2.1.2.5  Computing the Maximum Output Current
          6. 8.2.1.2.6  Selecting the Output Capacitor (C8 through C10)
          7. 8.2.1.2.7  Selecting the Input Capacitors (C2 and C7)
          8. 8.2.1.2.8  Setting the Output Voltage (R1 and R2)
          9. 8.2.1.2.9  Setting the Soft-Start Time (C7)
          10. 8.2.1.2.10 Selecting the Schottky Diode (D1)
          11. 8.2.1.2.11 Compensating the Control Loop (R3, C4, and C5)
        3. 8.2.1.3 Application Curves
      2. 8.2.2 TPS55340-Q1 SEPIC Converter
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1  Selecting the Switching Frequency (R4)
          2. 8.2.2.2.2  Duty Cycle
          3. 8.2.2.2.3  Selecting the Inductor (L1)
          4. 8.2.2.2.4  Calculating the Maximum Output Current
          5. 8.2.2.2.5  Selecting the Output Capacitor (C8 Through C10)
          6. 8.2.2.2.6  Selecting the Series Capacitor (C6)
          7. 8.2.2.2.7  Selecting the Input Capacitor (C2 and C7)
          8. 8.2.2.2.8  Selecting the Schottky Diode (D1)
          9. 8.2.2.2.9  Setting the Output Voltage (R1 and R2)
          10. 8.2.2.2.10 Setting the Soft-Start Time (C3)
          11. 8.2.2.2.11 Mosfet Rating Considerations
          12. 8.2.2.2.12 Compensating the Control Loop (R3 and C4)
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.1 Operation

If designed as a boost converter, the TPS55340-Q1 device regulates the output with current mode pulse-width-modulation (PWM) control. The PWM-control circuitry turns on the switch at the beginning of each oscillator clock cycle. The input voltage is applied across the inductor and stores the energy as inductor current ramps up. During this portion of the switching cycle, the load current is provided by the output capacitor. When the inductor current reaches a threshold level set by the error amplifier output, the power switch turns off and the external Schottky diode is forward biased to allow the inductor current to flow to the output. The inductor transfers stored energy to replenish the output capacitor and supply the load current. This operation repeats every switching cycle. The duty cycle of the converter is determined by the PWM-control comparator, which compares the error amplifier output and the current signal. The oscillator frequency is programmed by the external resistor or synchronized to an external clock signal.

A ramp signal from the oscillator is added to the inductor current ramp to provide slope compensation. Slope compensation is required to avoid subharmonic oscillation that is intrinsic to peak-current mode control at duty cycles higher than 50%. If the inductor value is too small, the internal slope compensation may not be adequate to maintain stability.

The PWM control feedback loop regulates the FB pin to a reference voltage through a transconductance error amplifier. The output of the error amplifier is connected to the COMP pin. An external RC-compensation network connected to the COMP pin is chosen for feedback loop stability and optimum transient response.