Achieving the performance the TPS6287x-Q1 devices are capable of requires proper PDN and PCB design. TI therefore recommends the user perform a power integrity analysis on their design. There are a number of commercially available power integrity software tools, and the user can use these tools to model the effects on performance of the PCB layout and passive components.

In addition to the use of power integrity tools, TI recommends the following basic principles:

• Place the input capacitors close to the VIN and GND pins. Position the input capacitors in order of increasing size, starting with the smallest capacitors closest to the VIN and GND pins. Use an identical layout for both VIN-GND pin pairs of the package, to gain maximum benefit from the butterfly configuration.
• Place the inductor close to the device and keep the SW node small.
• Connect the exposed thermal pad and the GND pins of the device together. Use multiple thermal vias to connect the exposed thermal pad of the device to one or more ground planes (TI's EVM uses nine 150-µm thermal vias).
• Use multiple power and ground planes.
• Route the VOSNS and GOSNS remote sense lines on the primary device as a differential pair and connect them to the lowest-impedance point of the PDN. If the desired connection point is not the lowest impedance point of the PDN, optimize the PDN until it is. Do not route the VOSNS and GOSNS close to any of the switch nodes.
• Connect the compensation components between COMP and AGND. Do not connect the compensation components directly to power ground.
• If possible, distribute the output capacitors evenly between the TPS6287x-Q1 device and the point-of-load, rather than placing them altogether in one place.
• Use multiple vias to connect each capacitor pad to the power and ground planes (TI's EVM typically uses four vias per pad).
• Use plenty of stitching vias to ensure a low impedance connection between different power and ground planes.