TPS65070 |
OMAP-L138 |
011 |
001 |
DCDC1= I/O, (3.3 V); enabled by EN_DCDC1
DCDC2= DVDD3318 (1.8 V or 3.3 V)
(DEFDCDC2=LOW: 1.8 V; DEFDCDC2=HIGH: 3.3 V)
DCDC3=core voltage CVDD
(DEFDCDC3=LOW: 1 V; DEFDCDC3=HIGH: 1.2 V)
LDO1= 1.8 V, delayed by external PMOS
LDO2= 1.2 V
PGOOD delay time (reset delay): 400ms <PGOODMASK>=08h: reset based on VDCDC2 |
TPS65072 |
Sirf Atlas 4 |
111 |
010 |
DCDC1=VDDIO (3.3 V)
DCDC2=VMEM (1.8 V)
DCDC3= VDD_PDN (1.2 V) driven by X_PWR_EN
LDO1=VDD_PLL (1.2 V)
LDO2=VDD_PRE (1.2 V)
EN_EXTLDO=VDDIO_RTC
PGOOD delay time (reset delay): 20 ms
<PGOODMASK>=10h: reset based on VDCDC1 |
TPS65073 |
OMAP3503
OMAP3515
OMAP3525
OMAP3530 |
101
Supporting
SYS-OFF mode |
001 |
Supporting SYS-OFF mode:
DCDC1=VDDS_WKUP_BG, VDDS_MEM, VDDS,
VDDS_SRAM (1.8 V)
DCDC2=VDDCORE (1.2 V)
DCDC3=VDD_MPU_IVA (1.2 V)
LDO1= VDDS_DPLL_DLL, VDDS_DPLL_PER (1.8 V)
LDO2=VDDS_MMC1 (1.8 V)
PGOOD delay time (reset delay): 400 ms
<PGOODMASK>=1Ch: based on VDCDC1, VDCDC2, VDCDC3 |
TPS650731 |
OMAP35xx |
110 |
011 |
DCDC1=VDDS_WKUP_BG, VDDS_MEM, VDDS,
VDDS_SRAM (1.8 V)
DCDC2=VDDCORE (1.2 V)
DCDC3=VDD_MPU_IVA (1.2 V)
LDO1=VDDS_DPLL_DLL (1.8 V)
LDO2=VDDA_DAC (1.8 V): OFF, enabled by I2C
PGOOD delay time (reset delay): 400 ms
<PGOODMASK>=1Ch: reset based on VDCDC1, VDCDC2, VDCDC3 |
TPS650732 |
AM3505
AM3517 |
110 |
001 |
DCDC1=VDDS1-5 (1.8 V)
DCDC2=VDDSHV (3.3 V)
DCDC3=VDD_CORE (1.2 V)
LDO1=VDDA1P8V (1.8 V)
LDO2=VDDS_DPLL (1.8 V)
PGOOD delay time (reset delay): 400 ms
<PGOODMASK>=1Ch: reset based on VDCDC1, VDCDC2, VDCDC3 |