JAJSFE6I July 2009 – May 2018 TPS65070 , TPS65072 , TPS65073 , TPS650731 , TPS650732
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
ADDRESS | NAME | SHORT DESCRIPTION |
---|---|---|
0x01h | PPATH1 | Power Path Controls |
0x02h | INT | Interrupt Reporting and Masking |
0x03h | CHGCONFIG0 | Battery Charger Configuration |
0x04h | CHGCONFIG1 | Battery Charger Configuration |
0x05h | CHGCONFIG2 | Battery Charger Configuration |
0x06h | CHGCONFIG3 | Battery Charger Configuration |
0x07h | ADCONFIG | ADC Configuration and Control |
0x08h | TSCMODE | Touch Screen Interface Control |
0x09h | ADRESULT_1 | ADC Result LSBs |
0x0Ah | ADRESULT_2 | ADC Result MSBs |
0x0Bh | PGOOD | Power Good Reporting |
0x0Ch | PGOODMASK | Power Good Masking |
0x0Dh | CON_CTRL1 | Sequence and Enable Control Bits for DCDCs and LDOs |
0x0Eh | CON_CTRL2 | Control Bits for Timers, UVLO, and DCDC2 / DCDC3 |
0x0Fh | CON_CTRL3 | Discharge Resistors and Force PWM Mode |
0x10h | DEFDCDC1 | Output Voltage Setting for DCDC1 |
0x11h | DEFDCDC2_LOW | Output Voltage Setting for DCDC2 if DEFDCDC2 is LOW |
0x12h | DEFDCDC2_HIGH | Output Voltage Setting for DCDC2 if DEFDCDC2 is HIGH |
0x13h | DEFDCDC3_LOW | Output Voltage Setting for DCDC3 if DEFDCDC3 is LOW |
0x14h | DEFDCDC3_HIGH | Output Voltage Setting for DCDC3 if DEFDCDC3 is HIGH |
0x15h | DEFSLEW | Define Slew Rate for DCDC2 & DCDC3 DVS |
0x16h | LDO_CTRL1 | Sequence and Output Voltage Control for LDOs |
0x17h | DEFLDO2 | Output Voltage Control for LDO2 |
0x18h | WLED_CTRL1 | wLED Control Bits |
0x19h | WLED_CTRL2 | wLED Control Bits |