JAJSFE6I July 2009 – May 2018 TPS65070 , TPS65072 , TPS65073 , TPS650731 , TPS650732
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SUPPLY CURRENT | ||||||
VINDCDC | Input voltage range for DC-DC converters | 2.8 | 6.3 | V | ||
IQ | Operating quiescent current
Total current into VSYS, VINDCDCx, VINLDO1/2 |
Only DCDC2, DCDC3 and LDO1 enabled, device in ON-mode; DCDC converters in PFM | 140 | µA | ||
Per DC/DC converter, PFM mode | 19 | 30 | ||||
For LDO1 or LDO2 (either one enabled) | 20 | 35 | ||||
For LDO1 and LDO2 (both enabled) | 34 | |||||
For wLED converter | 1.5 | mA | ||||
Per DC/DC converter, PWM mode | 2.5 | |||||
ISD | Shutdown current | All converters, LDOs, wLED driver and ADC disabled, no input voltage at AC and USB;
SYS voltage turned off |
8 | 12 | µA | |
VUVLO | Undervoltage lockout threshold | Voltage at the output of the power manager detected at pin SYS; falling voltage, voltage defined with <UVLO0>, <UVLO1> DEFAULT: 3 V | –2% | 2.8
3 3.1 3.25 |
2% | V |
Undervoltage lockout hysteresis | Rising voltage defined with <UVLO hysteresis>; DEFAULT: 500 mV | 360
450 |
mV | |||
Undervoltage lockout deglitch time | Due to internal delay | 4 | ms | |||
TSD | Thermal shutdown for DCDC converters, wLED driver and LDOs | Increasing junction temperature | 150 | °C | ||
Thermal shutdown hysteresis | Decreasing junction temperature | 20 | °C | |||
EN_DCDC1, EN_DCDC2, EN_DCDC3, DEFDCDC2, DEFDCDC3, SDAT, SCLK, EN_wLED (optional) | ||||||
VIH | High Level Input Voltage, EN_DCDC1, EN_DCDC2, EN_DCDC3, DEFDCDC2, DEFDCDC3, SDAT, SCLK, EN_wLED | 1.2 | VSYS | V | ||
VIL | Low Level Input Voltage, EN_DCDC1, EN_DCDC2, EN_DCDC3, DEFDCDC2, DEFDCDC3, SDAT, SCLK, EN_wLED | 0 | 0.4 | V | ||
IIN | Input bias current, EN_DCDC1, EN_DCDC2, EN_DCDC3, DEFDCDC2, DEFDCDC3, SDAT, SCLK | 0.01 | 1 | µA |