JAJSHS4B August   2019  – December 2019 TPS66020 , TPS66021

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     機能表
      1.      TPS6602x ブロック図
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Recommended Supply Load Capacitance
    5. 6.5  Thermal Information
    6. 6.6  PP5V Power Switch Characteristics
    7. 6.7  PPHV Power Switch Characteristics
    8. 6.8  Power Path Supervisory
    9. 6.9  VBUS LDO Characteristics
    10. 6.10 Thermal Shutdown Characteristics
    11. 6.11 Input-output (I/O) Characteristics
    12. 6.12 Power Consumption Characteristics
    13. 6.13 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 5-V Source (PP5V Power Path)
        1. 8.3.1.1 PP5V Current Limit
        2. 8.3.1.2 PP5V Reverse Current Protection (RCP)
      2. 8.3.2 20-V Sink (PPHV Power Path)
        1. 8.3.2.1 PPHV Soft Start
        2. 8.3.2.2 PPHV Reverse Current Protection (RCP)
      3. 8.3.3 Overtemperature Protection
      4. 8.3.4 VBUS Overvoltage Protection (OVP)
      5. 8.3.5 Power Management and Supervisory
        1. 8.3.5.1 Supply Connections
        2. 8.3.5.2 Power Up Sequences
          1. 8.3.5.2.1 Normal Power Up
          2. 8.3.5.2.2 Dead Battery Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 State Transitions
        1. 8.4.1.1 DISABLED State
        2. 8.4.1.2 SRC 1.5-A State
        3. 8.4.1.3 SRC 3-A State
        4. 8.4.1.4 SNK State
        5. 8.4.1.5 FRS (Fast Role Swap) State
      2. 8.4.2 SRC FAULT State
      3. 8.4.3 SNK FAULT State
      4. 8.4.4 Device Functional Mode Summary
      5. 8.4.5 Enabling the PP5V Source Path
      6. 8.4.6 Enabling the PPHV Sink Path
      7. 8.4.7 Fast Role Swap (FRS)
        1. 8.4.7.1 Overview
        2. 8.4.7.2 Fast Role Swap Use Cases
        3. 8.4.7.3 Fast Role Swap Sequence
      8. 8.4.8 Faults
        1. 8.4.8.1 Fault Types
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 External Current Reference Resistor (RIREF)
        2. 9.2.2.2 External VLDO Capacitor (CVLDO)
        3. 9.2.2.3 PP5V Power Path Capacitance
        4. 9.2.2.4 PPHV, VBUS Power Path Capacitance
        5. 9.2.2.5 VBUS TVS Protection (Optional)
        6. 9.2.2.6 VBUS Schottky Diode Protection (Optional)
        7. 9.2.2.7 VBUS Overvoltage Protection (Optional)
        8. 9.2.2.8 Dead Battery Support
        9. 9.2.2.9 Fast Role Swap (FRS) (Optional)
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 関連リンク
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ

Fast Role Swap (FRS) (Optional)

The TPS6602x supports Fast Role Swap operation as in the new Source, old Sink scenario shown in Figure 24. The PPHV power path represents the old Sink and the PP5V power path represents the new Source. During FRS, the PP5V power path of the TPS6602x has a much faster turn-on compared to normal operation, for example entering SRC 1P5A or SRC 3P0A states from the DISABLED state. This faster turn-on is required in order to meet the USB PD fast role swap timing requirements (tSrcFRSwap) for the new Source.

To enable FRS, the TPS6602x must first be operating as a Sink (SNK state). The TPS6602x must then transition to the FRS state by asserting EN1 high. EN1 is asserted high by the PD Controller as soon as possible once it has properly detected FRS signaling from its port partner on its CC line. The FRS signaling from the port partner to the PD Controller indicates that the port partner has lost its power and requires a fast role swap sequence to be performed.

It should be noted that the timing of when EN1 is asserted high relative to the port partner losing power is highly application, and implementation dependent. Some of these dependencies include:

  • Loss of power detection accuracy, margin and propagation delay of the port partner.
  • Timing from loss of power detection to FRS signaling transmitted on the CC line.
  • Detection by the PD Controller of the FRS signaling received on its CC line.
  • Assertion of a GPIO from the PD Controller after detection of the FRS signaling.

In systems that require good FRS performance, these should be optimized to minimize unnecessary delays from significantly impacting the turn-on of the new Source. Once the FRS state is entered, the TPS6602x will automatically handle the power role swap from Sink to Source as shown in Figure 25. In most applications, there is significant charge being stored in reserve while power is being provided. Upon loss of power, this charge is then used to supply power to the application until the FRS completes. As this charge depletes, the voltage on VBUS will decay at some rate based on the current load and the amount of charge that has been stored. USB PD requires that the new Source only be enabled once VBUS is detected below vSafe5V (maximum). Therefore, the amount of voltage that VBUS drops below vSafe5V will depend heavily on the amount of remaining charge and what current load is on VBUS, along with how fast the PP5V power path can enable. It should be noted that the PD Specification allows VBUS to be discharged completely to ground and is shown in Figure 32 typical response curve.