JAJSF89C March   2013  – December 2019 TPS84A20

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション概略図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Ordering Information
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Recommended Operating Conditions
    3. 7.3 Package Specifications
    4. 7.4 Electrical Characteristics
    5. 7.5 Thermal Information
  8. 8 Device Information
    1. 8.1      Functional Block Diagram
    2. Table 1. Pin Descriptions
  9. 9 Typical Characteristics (PVIN = VIN = 12 V)
  10. 10Typical Characteristics (PVIN = VIN = 5 V)
  11. 11Typical Characteristics (PVIN = 3.3 V, VIN = 5 V)
  12. 12Application Information
    1. 12.1  Adjusting the Output Voltage
    2. 12.2  Capacitor Recommendations for the TPS84A20 Power Supply
      1. 12.2.1 Capacitor Technologies
        1. 12.2.1.1 Electrolytic, Polymer-Electrolytic Capacitors
        2. 12.2.1.2 Ceramic Capacitors
        3. 12.2.1.3 Tantalum, Polymer-Tantalum Capacitors
      2. 12.2.2 Input Capacitor
      3. 12.2.3 Output Capacitor
    3. 12.3  Transient Response
    4. 12.4  Transient Waveforms
    5. 12.5  Application Schematics
    6. 12.6  VIN and PVIN Input Voltage
    7. 12.7  3.3 V PVIN Operation
    8. 12.8  Power Good (PWRGD)
    9. 12.9  Light Load Efficiency (LLE)
    10. 12.10 SYNC_OUT
    11. 12.11 Parallel Operation
    12. 12.12 Power-Up Characteristics
    13. 12.13 Pre-Biased Start-Up
    14. 12.14 Remote Sense
    15. 12.15 Thermal Shutdown
    16. 12.16 Output On/Off Inhibit (INH)
    17. 12.17 Slow Start (SS/TR)
    18. 12.18 Overcurrent Protection
    19. 12.19 Synchronization (CLK)
    20. 12.20 Sequencing (SS/TR)
    21. 12.21 Programmable Undervoltage Lockout (UVLO)
    22. 12.22 Layout Considerations
    23. 12.23 EMI
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントの更新通知を受け取る方法
    2. 13.2 サポート・リソース
    3. 13.3 商標
    4. 13.4 静電気放電に関する注意事項
    5. 13.5 Glossary
  14. 14メカニカル、パッケージ、および注文情報
    1. 14.1 Tape and Reel Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RVQ|42
サーマルパッド・メカニカル・データ
発注情報

7.4 Electrical Characteristics

Over –40°C to 85°C free-air temperature, PVIN = VIN = 12 V, VOUT = 1.8 V, IOUT = 10 A,
CIN = 0.1 µF + 2 x 22 µF ceramic + 100 µF bulk, COUT = 4 x 47 µF ceramic (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IOUT Output current TA = 85°C, natural convection 0 (1) 10 A
VIN Input bias voltage range Over output current range 4.5 17 V
PVIN Input switching voltage range Over output current range 2.95 (3) 17 (4) V
UVLO VIN Undervoltage lockout VIN Increasing 4.0 4.5 V
VIN Decreasing 3.5 3.85
VOUT(adj) Output voltage adjust range Over output current range 0.6 5.5 V
VOUT Set-point voltage tolerance TA = 25°C, IOUT = 0 A ±1% (2)
Temperature variation –40°C ≤ TA ≤ +85°C, IOUT = 0 A ±0.2%
Line regulation Over input voltage range ±0.1%
Load regulation Over output current range ±0.2%
Total output voltage variation Includes set-point, line, load, and temperature variation ±1.5% (2)
η Efficiency PVIN = VIN = 12 V
IO = 5 A  		 VOUT = 5.0 V, fSW = 1 MHz 93 %
VOUT = 3.3 V, fSW = 750 kHz 92 %
VOUT = 2.5 V, fSW = 750 kHz 90 %
VOUT = 1.8 V, fSW = 500 kHz 89 %
VOUT = 1.2 V, fSW = 300 kHz 86 %
VOUT = 0.9 V, fSW = 250 kHz 84 %
VOUT = 0.6 V, fSW = 200 kHz 81 %
PVIN = VIN = 5 V
IO = 5 A  		 VOUT = 3.3 V, fSW = 750 kHz 94 %
VOUT = 2.5 V, fSW = 750 kHz 93 %
VOUT = 1.8 V, fSW = 500 kHz 92 %
VOUT = 1.2 V, fSW = 300 kHz 89 %
VOUT = 0.9 V, fSW = 250 kHz 87 %
VOUT = 0.6 V, fSW = 200 kHz 83 %
Output voltage ripple 20 MHz bandwidth 14 mVP-P
ILIM Current limit threshold ILIM pin open 15 A
ILIM pin to AGND 12 A
Transient response 1.0 A/µs load step from
25 to 75% IOUT(max) 		 Recovery time 100 µs
VOUT over/undershoot 80 mV
VINH Inhibit threshold voltage Inhibit High Voltage 1.3 open(5) V
Inhibit Low Voltage -0.3 1.1
IINH INH Input current VINH < 1.1 V -1.15 μA
INH Hysteresis current VINH > 1.3 V -3.3 μA
II(stby) Input standby current INH pin to AGND 2 10 µA
Power Good PWRGD Thresholds VOUT rising Good 95%
Fault 108%
VOUT falling Fault 91%
Good 104%
PWRGD Low Voltage I(PWRGD) = 0.5 mA 0.3 V
fSW Switching frequency RRT = 169 kΩ 400 500 600 kHz
fCLK Synchronization frequency CLK Control 200 1200 kHz
VCLK-H CLK High-Level 2.0 5.5 V
VCLK-L CLK Low-Level 0.5 V
DCLK CLK Duty Cycle 20 50 80 %
Thermal Shutdown Thermal shutdown 175 °C
Thermal shutdown hysteresis 10 °C
CIN External input capacitance Ceramic 44 (6) µF
Non-ceramic 100 (6)
COUT External output capacitance Ceramic 47(7) 200 1500 µF
Non-ceramic 220 (7) 5000 (8)
Equivalent series resistance (ESR) 35 mΩ
(1) See Light Load Efficiency (LLE) section for more information for output voltages < 1.5 V.
(2) The stated limit of the set-point voltage tolerance includes the tolerance of both the internal voltage reference and the internal adjustment resistor. The overall output voltage tolerance will be affected by the tolerance of the external RSET resistor.
(3) The minimum PVIN is 2.95 V or (VOUT + 0.7 V), whichever is greater. See Table 8 for more details.
(4) The maximum PVIN voltage is 17 V or (22 x VOUT), whichever is less. See Table 8 for more details.
(5) Value when no voltage divider is present at the INH/UVLO pin. This pin has an internal pull-up. If it is left open, the device operates when input power is applied. A small, low-leakage MOSFET is recommended for control. Do not tie this pin to VIN.
(6) A minimum of 44 µF of external ceramic capacitance is required across the input (VIN and PVIN connected) for proper operation. An additional 100 µF of bulk capacitance is recommended. It is also recommended to place a 0.1-µF ceramic capacitor directly across the PVIN and PGND pins of the device. Locate the input capacitance close to the device. When operating with split VIN and PVIN rails, place 4.7µF of ceramic capacitance directly at the VIN pin. See Table 5 for more details.
(7) The amount of required output capacitance varies depending on the output voltage (see Table 4). The amount of required capacitance must include at least 1x 47 µF ceramic capacitor. Locate the capacitance close to the device. Adding additional capacitance close to the load improves the response of the regulator to load transients. See Table 4 and Table 5 more details.
(8) The maximum output capacitance of 5000 µF includes the combination of both ceramic and non-ceramic capacitors.