JAJSHS0C March 2019 – March 2021 TPS92682-Q1
PRODUCTION DATA
The device incorporates 65-V input voltage rated linear regulators to generate the 7.5-V (typical) VCC bias supply, the 5-V (typical) VDD supply, and other internal reference voltages. The device monitors the VCC output to implement UVLO protection. Operation is enabled when VCC exceeds the 4.5-V (typ) threshold and is disabled when VCC drops below the 4.1-V (typical) threshold. The UVLO comparator provides a hysteresis to avoid chatter during transitions. The UVLO thresholds are internally fixed and cannot be adjusted. An internal current limit circuit is implemented to protect the device during VCC pin short-circuit conditions. The VCC supply powers the internal circuitry and the N-channel gate driver outputs, GATEx. Place a bypass capacitor in the range of 2.2 μF to 4.7 μF across the VCC output and GND to ensure proper operation. The regulator operates in dropout when input voltage VIN falls below 7.5 V. The VCC is a regulated output of the internal regulator and is not recommended to be driven with an external power supply.
The internal VDD regulator is used to generate supply voltage for various internal analog and digital circuits. The supply current is internally limited to protect the device from output overload and short-circuit conditions. Place a bypass capacitor in the range of 2.2 μF to 4.7 μF across the VDD output to GND to ensure proper operation. The POR circuit of the device is placed at the output of the VDD regulator. The POR rise and fall thresholds are provided in the Electrical Characteristics.