JAJSHS0C March   2019  – March 2021 TPS92682-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Device Enable
      2. 7.3.2  Internal Regulator and Undervoltage Lockout (UVLO)
      3. 7.3.3  Oscillator
      4. 7.3.4  Spread Spectrum Function
      5. 7.3.5  Gate Driver
      6. 7.3.6  Rail-to-Rail Current Sense Amplifier
      7. 7.3.7  Transconductance Error Amplifier
      8. 7.3.8  Switch Current Sense
      9. 7.3.9  Slope Compensation
      10. 7.3.10 ILED Setting in CC Mode
      11. 7.3.11 Output Voltage Setting in CV Mode
      12. 7.3.12 PWM Dimming
      13. 7.3.13 P-Channel FET Gate Driver Output
      14. 7.3.14 Soft Start
      15. 7.3.15 Two-Phase Operation
        1. 7.3.15.1 Current Sharing In Two-Phase
      16. 7.3.16 Faults and Diagnostics
        1. 7.3.16.1  Main Fault Timer (MFT)
        2. 7.3.16.2  OV Fault
        3. 7.3.16.3  UV Fault
        4. 7.3.16.4  ILIM Fault
        5. 7.3.16.5  UVLO
        6. 7.3.16.6  ILED Over Current (OC)
        7. 7.3.16.7  ILED Undercurrent (UC)
        8. 7.3.16.8  ISNOPEN, FBOPEN, and RTOPEN Faults
        9. 7.3.16.9  TW and TSD
        10. 7.3.16.10 COMPx Pull-Down and Comp-Low signal
    4. 7.4 Device Functional Modes
      1. 7.4.1 POR Mode
      2. 7.4.2 Normal Operation
      3. 7.4.3 Limp Home
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
      2. 7.5.2 Command Frame
      3. 7.5.3 Response Frame
        1. 7.5.3.1 Read Response Frame Format
        2. 7.5.3.2 Write Response Frame Format
        3. 7.5.3.3 Write Error/POR Frame Format
      4. 7.5.4 SPI Error
    6. 7.6 TPS92682 Registers
      1. 7.6.1  EN Register
      2. 7.6.2  CFG1 Register
      3. 7.6.3  CFG2 Register
      4. 7.6.4  SWDIV Register
      5. 7.6.5  ISLOPE Register
      6. 7.6.6  FM Register
      7. 7.6.7  SOFTSTART Register
      8. 7.6.8  CH1IADJ Register
      9. 7.6.9  CH2IADJ Register
      10. 7.6.10 PWMDIV Register
      11. 7.6.11 CH1PWML Register
      12. 7.6.12 CH1PWMH Register
      13. 7.6.13 CH2PWML Register
      14. 7.6.14 CH2PWMH Register
      15. 7.6.15 ILIM Register
      16. 7.6.16 IFT Register
      17. 7.6.17 MFT Register
      18. 7.6.18 FLT1 Register (read only)
      19. 7.6.19 FLT2 Register (read only)
      20. 7.6.20 FEN1 Register
      21. 7.6.21 FEN2 Register
      22. 7.6.22 FLATEN Register
      23. 7.6.23 OV Register
      24. 7.6.24 LHCFG Register
      25. 7.6.25 LHCH1IADJ Register
      26. 7.6.26 LHCH2IADJ Register
      27. 7.6.27 LHCH1PWML Register
      28. 7.6.28 LHCH1PWMH Register
      29. 7.6.29 LHCH2PWML Register
      30. 7.6.30 LHCH2PWMH Register
      31. 7.6.31 LHILIM Register
      32. 7.6.32 LHIFT Register
      33. 7.6.33 LHMFT Register
      34. 7.6.34 LHFEN1 Register
      35. 7.6.35 LHFEN2 Register
      36. 7.6.36 LHFLATEN Register
      37. 7.6.37 LHOV Register
      38. 7.6.38 CAL Register
      39. 7.6.39 RESET Register
  8. 8 Application and Implementation
    1. 8.1 Application Information General Design Considerations
      1. 8.1.1 Switching Frequency, fSW
      2. 8.1.2 Duty Cycle Considerations
      3. 8.1.3 Main Power MOSFET Selection
      4. 8.1.4 Rectifier Diode Selection
      5. 8.1.5 Switch Current Sense Resistor
      6. 8.1.6 Slope Compensation
      7. 8.1.7 Soft Start
    2. 8.2 Application Information CC Mode
      1. 8.2.1 Inductor Selection
      2. 8.2.2 Output Capacitor Selection
      3. 8.2.3 Input Capacitor Selection
      4. 8.2.4 Programming LED Current
      5. 8.2.5 Feedback Compensation
      6. 8.2.6 Overvoltage and Undervoltage Protection
      7. 8.2.7 Series P-Channel MOSFET Selection
      8. 8.2.8 Programming Example for Two-Channel CC Mode
    3. 8.3 Typical Application CV Mode
      1. 8.3.1 Inductor Selection
      2. 8.3.2 Output Capacitor Selection
      3. 8.3.3 Input Capacitor Selection
      4. 8.3.4 Programming Output Voltage VOUT
      5. 8.3.5 Feedback Compensation
      6. 8.3.6 Overvoltage and Undervoltage Protection
      7. 8.3.7 Programing Example for Two-Phase CV BOOST
    4. 8.4 Typical Application CC Mode
      1. 8.4.1 CC Boost Design Requirements
      2. 8.4.2 CC Boost Detailed Design Procedure
        1. 8.4.2.1  Calculating Duty Cycle
        2. 8.4.2.2  Setting Switching Frequency
        3. 8.4.2.3  Setting Dither Modulation Frequency
        4. 8.4.2.4  Inductor Selection
        5. 8.4.2.5  Output Capacitor Selection
        6. 8.4.2.6  Input Capacitor Selection
        7. 8.4.2.7  Main N-Channel MOSFET Selection
        8. 8.4.2.8  Rectifier Diode Selection
        9. 8.4.2.9  Setting ILED and Selecting RCS
        10. 8.4.2.10 Setting Switch Current Limit
        11. 8.4.2.11 Slope Compensation
        12. 8.4.2.12 Compensator Parameters
        13. 8.4.2.13 Overvoltage Protection
        14. 8.4.2.14 Series P-Channel MOSFET Selection
      3. 8.4.3 CC Buck-Boost Design Requirements
      4. 8.4.4 CC Buck-Boost Detailed Design Procedure
        1. 8.4.4.1  Calculating Duty Cycle
        2. 8.4.4.2  Setting Switching Frequency
        3. 8.4.4.3  Setting Dither Modulation Frequency
        4. 8.4.4.4  Inductor Selection
        5. 8.4.4.5  Output Capacitor Selection
        6. 8.4.4.6  Input Capacitor Selection
        7. 8.4.4.7  Main N-Channel MOSFET Selection
        8. 8.4.4.8  Rectifier Diode Selection
        9. 8.4.4.9  Setting ILED and Selecting RCS
        10. 8.4.4.10 Setting Switch Current Limit
        11. 8.4.4.11 Slope Compensation
        12. 8.4.4.12 Compensator Parameters
        13. 8.4.4.13 Overvoltage Protection
      5. 8.4.5 PWM Dimming Consideration
      6. 8.4.6 Application Curves
    5. 8.5 Typical Application CV Mode
      1. 8.5.1 CV Design Requirements
      2. 8.5.2 Detailed Design Procedure
        1. 8.5.2.1  Calculating Duty Cycle
        2. 8.5.2.2  Setting Switching Frequency
        3. 8.5.2.3  Setting Dither Modulation Frequency
        4. 8.5.2.4  Inductor Selection
        5. 8.5.2.5  Output Capacitor Selection
        6. 8.5.2.6  Input Capacitor Selection
        7. 8.5.2.7  Main N-Channel MOSFET Selection
        8. 8.5.2.8  Rectifier Diode Selection
        9. 8.5.2.9  Programming VOUT
        10. 8.5.2.10 Setting Switch Current Limit
        11. 8.5.2.11 Slope Compensation
        12. 8.5.2.12 Compensator Parameters
        13. 8.5.2.13 Overvoltage Protection
      3. 8.5.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

–40°C < TJ < 150°C, VIN= 14V, VIADJDACx = 0xDF, CVCC = 1μF, CVDD = 1μF, CCOMP = 2.2nF, RCS = 100mΩ, RT = 50kΩ, VPWM = 5V, no load on GATE and PDRV, DIV=4 (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
INPUT VOLTAGE (VIN)
IIN-SHDNInput shutdown currentVEN = 0 V, VCSP = VCSN = VPDRV = 0 V10µA
VEN = 0 V, VCSP = 14 V10.5
IIN-STBYInput standby currentSoftware EN1 and EN2 = 0, VPWM1 = VPWM2 = 0 V2.3mA
IIN-SWSupply switching currentVCC=7.5V, CGATEx = 1nF, Both channels are switching10mA
VCC BIAS SUPPLY
VCCUVLOSupply under-voltage protectionVCC rising threshold,
VVIN = 8 V		4.54.9V
VCC falling threshold,
VVIN = 8 V		3.74.1V
Hysteresis411mV
VCC(REG)VCC regulation voltageNo load77.58V
IVCC(LIMIT)VCC current limitVVCC = 0 V40mA
VCCDOVCC LDO dropout voltageIVCC = 30 mA, VVIN = 4.5 V300475mV
VDD BIAS SUPPLY
VDD(REG)VDD regulation voltageNo load4.8555.25V
VDD(POR-RISE)VDD rising thresholdVVIN = 5 V4.1V
VDD(POR-FALL)VDD falling thresholdVVIN = 5 V2.58V
VDDDOVDD LDO dropout voltageIVDD = 15 mA, VVIN = 4.5 V400mV
IVDD(LIMIT)VDD current limitVVDD = 0 V303950mA
ENABLE INPUT
VENEN voltage threshold1.121.211.3V
VEN-HYSEN pin hysteresisDifference between rising and falling threshold100mV
IENEN PIN input bias currentVEN = 14 V5µA
OSCILLATOR
fSWSwitching frequencyRT = 200kΩ, DIV=485100115kHz
RT = 50kΩ, DIV=4340400460kHz
VRTRT PIN voltage1V
SPREAD SPECTRUM DAC
DACDT-BITsInternal DAC resolution8Bits
DACDT-MAXDAC maximum voltage1.156V
DACDT-MINDAC minimum voltage855mV
GATE DRIVER
RGHDriver pull-up resistanceIGATE = –10 mA5.111.2Ω
RGLDriver pull-down resistanceIGATE = 10 mA4.110.5Ω
SWITCH CURRENT SENSE and ILIMIT
VILIM(THR)ILIM threshold PWM = LOWVPWMx= 0 V, CHxILIM = XX649711769mV
ILIM threshold PWM = HIGHVPWMx= 5 V, CHxILIM = 11228253277mV
VPWMx= 5 V, CHxILIM = 10132151171mV
VPWMx= 5 V, CHxILIM = 0182100.6119mV
VPWMx= 5 V, CHxILIM = 005775.293mV
tIS(BLANK)Leading edge blankingCHxLEB = 075ns
CHxLEB = 1150ns
tILIMIT(DELAY)ISx to GATEx delay86ns
PWM COMPARATOR
DMAXMaximum duty cycle90%
VLVx-DeltaDifference between CH1 and CH2 PWM comparator offset–17.517.5mV
ILVxIS level shift bias currentNo slope compensation added40µA
TPWM-DeltaTurn-off propagation delay from input of PWM comp. to gate output100ns
TPWMDEL-DeltaDifference between CH1 and CH2 PWM comp. propagation delay–3030ns
CURRENT SENSE AMPLIFIER (CSP, CSN)
V(CSP-CSN)xCurrent Sense REG VoltageVCSP(CM) = 14 V, IADJDAC = 0×FF165.8172.7179.6mV
VCSP(CM) = 14V, IADJDAC = 0x9596.5100.8104.5mV
VCSP(CM) = 14V, IADJDAC = 0×0F10.3mV
CS(BW)Current sense unity gain bandwidth500kHz
GCSCurrent Sense Gain = VIADJ/V(CSP-CSN)VCS = 150 mV, VCSP = 60 V14V/V
K(OCP)Ratio of over-current detection threshold to VIADJK(OCP) = V(OCP-THR)/VIADJ1.411.531.66V/V
K(UC)Ratio of under-current detection threshold to VIADJK(UC) = V(UC-THR)/VIADJ0.5V/V
ICSP(BIAS)CSP bias currentVCSP = VCSN = VPDRV = 14 V59µA
ICSN(BIAS)CSN bias currentVCSP = VCSN = VPDRV = 14 V59µA
SSDAC
DACSS-BITsInternal DAC resolution8Bits
DACSS-FSDAC full scale voltage2.8V
CALDAC
DACCAL-BITsSwitch current sense calibration DAC3Bits
DACCAL-RESOffset-per-Bit applied to the switch current sense2.5mV
FAULT FLAG ( FLTx)
R( FLT)Open-drain pull down resistance36Ω
VIADJDAC
DACADJ-BITsInternal DAC resolution8Bits
DACADJ-FSDAC full scale voltage2.322.42.48V
ERROR AMPLIFIER (COMP)
gMTransconductanceHG = 0122µA/V
HG = 1914
ICOMP(SRC)COMP source current capacityIADJx = 0×95, V(CSP-CSN) = 0 V, HG = 0129µA
IADJx = 0×95, V(CSP-CSN) = 0 V, HG = 1777
ICOMP(SINK)COMP sink current capacityIADJx = 0×00, V(CSP-CSN) = 0.1 V, HG = 0129µA
IADJx = 0×00, V(CSP-CSN) = 0.1 V, HG = 1783
EA(BW)Error amplifier bandwidthGain = –3 dB, HG = 05MHz
Gain = –3 dB, HG = 11
VCOMP(RST)VCOMP reset voltage100mV
RCOMP(DCH)COMPx discharge FET RDSON248Ω
RCOMP(DIFF)COMP1 to COMP2 short path resistance300Ω
SLOPEDAC
DACSLP-FSDAC full scale voltage0.36V
VFB
VFBERRRegulation voltage error–44%
VFBBIASVFB pin pull up bias current200nA
OVDAC
VOV(THR)OV limit threshold, 0%CHxOVDAC = 0001.21.2371.27V
OV limit threshold, 2.5%CHxOVDAC = 0011.268V
OV limit threshold, 5%CHxOVDAC = 0101.299V
OV limit threshold, 7.5%CHxOVDAC = 0111.329V
OV limit threshold, 10%CHxOVDAC = 1001.36V
OV limit threshold, 12.5%CHxOVDAC = 1011.391V
OV limit threshold, 15%CHxOVDAC = 1101.422V
OV limit threshold, 20%CHxOVDAC = 1111.483V
IOV-HYSOV hysteresis current11.520.528.5µA
UV (Output Under Voltage)
VUV(THR)Under voltage protection threshold4053.267mV
tUV(BLANK)Under voltage blanking period5µs
DIGITAL INPUTs (PWMx, SYNC, LH, SSN, SCK, MOSI)
IBIASInput bias currentExcept PWM inputs1µA
VTINPUT-FALLFalling threshold0.7V
VTINPUT-RISERising threshold1.85V
PWM INPUT (PWM)
RPWM(PD)PWM pull-down resistance10MΩ
tDLY(RISE)PWM rising to PDRV delayCPDRV = 1 nF235ns
tDLY(FALL)PWM falling to PDRV delayCPDRV = 1 nF222ns
PFET GATE DRIVE
VPDRV(OFF)PDRV off-state voltageVCSP = 14 V14V
VPDRV(ON)PDRV on-state voltageVCSP = 14 V7.34V
IPDRV(SINK)PDRV sink currentVCSP – VPDRV = 5 V, pulsed < 100 µs29mA
RPDRVPDRV pull up resistanceVCSP – VPDRV = 0 V, pulsed < 100 µs83.5Ω
SPI INTERFACE
VOL-MISOOutput low voltage thresholdI(MISO) = 10 mA0.25V
RDS-MISO25Ω
CMISO10pF
tSS-SUSSN setup timeFalling edge of SSN to 1st SCK rising edge500ns
tSS-HSSN hold timeFalling edge of 16th SCK to SSN rising edge250ns
tSS-HISSN high timeTime SSN must remain high between transactions1µs
tSCKSCK periodClock period500ns
DSCKSCK duty cycleClock duty cycle4060%
tMOSI-SUMOSI setup timeMOSI valid to rising edge SCK125ns
tMOSI-HMOSI hold timeMOSI valid after rising edge SCK140ns
tMISO-HIZMISO tristate timeTime to tristate MISO after SSN rising edge110320ns
tMISO-HLMISO valid high-to-lowTime to place valid "0" on MISO after falling SCK edge.320ns
tMISO-LHMISO valid low-to-highTime to tri-state MISO after falling SCK edge. tRC is the time added by the application total capacitance and resistance.320+tRCns
TZO-HLMISO drive time high-to-lowSSN Falling Edge to MISO Falling320ns