JAJSEW6B February   2018  – February 2024 UCC21222

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety-Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Switching Characteristics
    11. 5.11 Thermal Derating Curves
    12. 5.12 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Minimum Pulses
    2. 6.2 Propagation Delay and Pulse Width Distortion
    3. 6.3 Rising and Falling Time
    4. 6.4 Input and Disable Response Time
    5. 6.5 Programmable Dead Time
    6. 6.6 Power-Up UVLO Delay to OUTPUT
    7. 6.7 CMTI Testing
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD, VCCI, and Undervoltage Lock Out (UVLO)
      2. 7.3.2 Input and Output Logic Table
      3. 7.3.3 Input Stage
      4. 7.3.4 Output Stage
      5. 7.3.5 Diode Structure in the UCC21222
    4. 7.4 Device Functional Modes
      1. 7.4.1 Disable Pin
      2. 7.4.2 Programmable Dead Time (DT) Pin
        1. 7.4.2.1 DT Pin Tied to VCCI or DT Pin Left Open
        2. 7.4.2.2 Connecting a Programming Resistor between DT and GND Pins
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Designing INA/INB Input Filter
        3. 8.2.2.3 Select Dead Time Resistor and Capacitor
        4. 8.2.2.4 Select External Bootstrap Diode and its Series Resistor
        5. 8.2.2.5 Gate Driver Output Resistor
        6. 8.2.2.6 Estimating Gate Driver Power Loss
        7. 8.2.2.7 Estimating Junction Temperature
        8. 8.2.2.8 Selecting VCCI, VDDA/B Capacitor
          1. 8.2.2.8.1 Selecting a VCCI Capacitor
          2. 8.2.2.8.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 8.2.2.8.3 Select a VDDB Capacitor
        9. 8.2.2.9 Application Circuits with Output Stage Negative Bias
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Component Placement Considerations
      2. 10.1.2 Grounding Considerations
      3. 10.1.3 High-Voltage Considerations
      4. 10.1.4 Thermal Considerations
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 サード・パーティ製品に関する免責事項
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.10 Switching Characteristics

VVCCI = 3.3 V or 5.5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V, 1-µF capacitor from VDDA and VDDB to VSSA and VSSB, load capacitance COUT = 0 pF, TA = –40°C to +125°C unless otherwise noted(1).
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
tRISEOutput rise time
See Figure 6-4.		CVDD = 10 µF, COUT = 1.8 nF,
VVDDA, VVDDB = 12 V, f = 1 kHz		516ns
tFALLOutput fall time
See Figure 6-4.		CVDD = 10 µF, COUT = 1.8 nF ,
VVDDA, VVDDB = 12 V, f = 1 kHz		612ns
tPWminMinimum input pulse width that passes to output
See Figure 6-1 and Figure 6-2.		Output does not change the state if input signal less than tPWmin1020ns
tPDHLPropagation delay at falling edge
See Figure 6-3.		INx high threshold, VINH, to 10% of the output2840ns
tPDLHPropagation delay at rising edge
See Figure 6-3.		INx low threshold, VINL, to 90% of the output2840ns
tPWDPulse width distortion in each channel
See Figure 6-3.		|tPDLHA – tPDHLA|, |tPDLHB– tPDHLB|5.5ns
tDMPropagation delays matching,
|tPDLHA – tPDLHB|, |tPDHLA – tPDHLB|
See Figure 6-3.		f = 250kHz5ns
tVCCI+ to OUTVCCI Power-up Delay Time: UVLO Rise to OUTA, OUTB,
See Figure 6-7.		INA or INB tied to VCCI40µs
tVDD+ to OUTVDDA, VDDB Power-up Delay Time: UVLO Rise to OUTA, OUTB
See Figure 6-8.		INA or INB tied to VCCI22
|CMH|High-level common-mode transient immunity
See Section 6.7.		Slew rate of GND vs. VSSA/B, INA and INB both are tied to GND or VCCI; VCM=1000 V;100V/ns
|CML|Low-level common-mode transient immunity
See Section 6.7.		Slew rate of GND vs. VSSA/B, INA and INB both are tied to GND or VCCI; VCM=1000 V;100
(1) Parameters with only a typical value are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's product warranty.