JAJSBF8B June   2011  – April 2018 TPS54478

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     効率
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Slope Compensation and Output Current
      3. 7.3.3  Bootstrap Voltage (BOOT) and Low Dropout Operation
      4. 7.3.4  Error Amplifier
      5. 7.3.5  Voltage Reference
      6. 7.3.6  Adjusting the Output Voltage
      7. 7.3.7  Enable and Adjusting Undervoltage Lockout
      8. 7.3.8  Slow Start / Tracking Pin
      9. 7.3.9  Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      10. 7.3.10 Overcurrent Protection
      11. 7.3.11 START-UP into Prebiased Output
      12. 7.3.12 Synchronize Using the RT/CLK Pin
      13. 7.3.13 Power Good (PWRGD Pin)
      14. 7.3.14 Overvoltage Transient Protection
      15. 7.3.15 Thermal Shutdown
      16. 7.3.16 Small Signal Model for Loop Response
      17. 7.3.17 Simple Small Signal Model for Peak Current Mode Control
      18. 7.3.18 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 PWM Operation
      2. 7.4.2 Standby Operation
    5. 7.5 Programming
      1. 7.5.1 Sequencing
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Selecting the Switching Frequency
        2. 8.2.2.2 Output Inductor Selection
        3. 8.2.2.3 Output Capacitor
        4. 8.2.2.4 Input Capacitor
        5. 8.2.2.5 Slow Start Capacitor
        6. 8.2.2.6 Bootstrap Capacitor Selection
        7. 8.2.2.7 Output Voltage and Feedback Resistors Selection
        8. 8.2.2.8 Compensation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation Estimate
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 11.1.2 WEBENCH®ツールによるカスタム設計
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

6.5 Electrical Characteristics

TJ = –40°C to 150°C, VIN = 2.95 to 6 V (unless otherwise noted)
DESCRIPTION TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage 2.95 6.0 V
Input under voltage lockout threshold No voltage hysteresis 2.6 V
Shutdown supply current EN = 0 V, 25°C, 2.95 V ≤ VIN ≤ 6 V 0.7 2.5 μA
Quiescent Current - Iq VSENSE = 0.7 V, VIN = 5 V, 25°C, RT = 78.7 kΩ 525 700 μA
ENABLE AND UVLO (EN PIN)
Enable threshold Rising 1.30 V
Falling 1.21
Input current Enable threshold + 50 mV –3.4 μA
Enable threshold – 50 mV –0.64
VOLTAGE REFERENCE (VSENSE PIN)
Voltage Reference 2.95 V ≤ VIN ≤ 6 V, –40°C <TJ< 150°C 0.594 0.600 0.606 V
MOSFET
High side switch resistance BOOT-PH = 5 V 30 60 mΩ
BOOT-PH = 3.3 V 37 70
Low side switch resistance VIN = 5 V 30 60 mΩ
VIN = 3.3 V 37 70
ERROR AMPLIFIER
Input current 7 nA
Error amplifier transconductance (gm) –2 μA < I(COMP)< 2 μA, V(COMP) = 1 V 225 μmhos
Error amplifier transconductance (gm) during slow start –2 μA < I(COMP)< 2 μA, V(COMP) = 1 V,
Vsense = 0.4 V		 77 μmhos
Error amplifier source/sink V(COMP) = 1 V, 100 mV overdrive ±20 μA
COMP to Iswitch gm 14 A/V
CURRENT LIMIT
Current limit threshold VIN = 6V, Fs = 500 KHz 5.2 6.5 8.2 A
Cycles before entering hiccup 512 Cycles
Cycles of converter in off state during hiccup 16384 Cycles
Low side Fet reverse current limit 3.1 A
THERMAL SHUTDOWN
Thermal shutdown 165 °C
Hysteresis 15 °C
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching frequency range using RT mode 200 2000 kHz
Switching frequency R(RT/CLK) = 78.7 kΩ 400 500 600 kHz
Switching frequency range using CLK mode 300 2000 kHz
Minimum CLK pulse width 75 ns
RT/CLK voltage R(RT/CLK) = 78.7 kΩ 0.5 V
RT/CLK high threshold 1.6 2.2 V
RT/CLK low threshold 0.4 0.6 V
RT/CLK falling edge to PH rising edge delay Measure at 500 kHz with RT resistor in series 75 ns
PLL lock in time Measure at 500 kHz 14 μs
PH (PH PIN)
Minimum On time Measured at 50% points on PH, VIN = 5 V, IOUT = 2 A 100 ns
Measured at 50% points on PH, VIN = 5 V,
IOUT = 0 A		 120
Minimum Off time Prior to skipping off pulses, VIN = 5 V,
IOUT = 2 A		 110 ns
Rise Time VIN = 5 V, 4 A 1.5 V/ns
Fall Time 1.5
BOOT (BOOT PIN)
BOOT Charge Resistance VIN = 5 V 15 Ω
BOOT-PH UVLO VIN = 2.95 V 2.2 V
SLOW START AND TRACKING (SS/TR PIN)
SS voltage threshold (VSSTHR) 0.15 V
Charge Current V(SS/TR)< VSSTHR 45 μA
V(SS/TR)> VSSTHR 2.2
SS/TR to VSENSE matching V(SS/TR) = 0.3 V 65 mV
SS/TR to reference crossover 98% normal 0.86 V
SS/TR discharge voltage (Overload) VSENSE = 0 V 2.5 mV
SS/TR discharge current (Overload) VSENSE = 0 V, V(SS/TR) = 0.4 V 900 µA
SS discharge current (UVLO, EN, Thermal fault) VIN = 5 V, V(SS) = 0.5 V 1.16 mA
POWER GOOD (PWRGD PIN)
VSENSE threshold VSENSE falling (Fault) 93 % Vref
VSENSE rising (Good) 95
VSENSE rising (Fault) 107
VSENSE falling (Good) 105
Hysteresis VSENSE falling 2 % Vref
Output high leakage VSENSE = VREF, V(PWRGD) = 5.5 V 7 nA
On resistance VIN = 2.95 V 56 120 Ω
Output low I(PWRGD) = 3 mA 0.2 0.3 V
Minimum VIN for valid output V(PWRGD)< 0.5 V at 100 μA 1.2 1.6 V