JAJSDN3F December 2016 – April 2024 TDP158
PRODUCTION DATA
The TDP158 local I2C interface is enabled when I2C_EN is high. The SCL_CTL and SDA_CTL terminals are used for I2C clock and data respectively. The TDP158 I2C interface conforms to the two-wire serial interface defined by the I2C Bus Specification, Version 2.1 (January 2000), and supports the fast mode transfer up to 400Kbps. The device address byte is the first byte received following the START condition from the controller device. The 7 bit device address for TDP158 decides by the combination of A0/EQ1 and A1/EQ2. Table 7-6 provides the TDP158 target address.
A1/A0 | Bit 7 (MSB) | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 (W/R) | HEX |
---|---|---|---|---|---|---|---|---|---|
00 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0/1 | BC/BD |
01 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0/1 | BA/BB |
10 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0/1 | B8/B9 |
11 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0/1 | B6/B7 |
The local I2C is 5-V tolerant, and no additional circuitry required. Local I2C buses run at 400kHz supporting fast-mode I2C operation.
The following procedure is followed to write to the TDP158 I2C registers:
The following procedure is followed to read the TDP158 I2C registers:
Upon reset, the TDP158 sub-address will always be set to 0x00. When no sub-address is included in a read operation, the TDP158 sub-address will increment from previous acknowledged read or write data byte. If it is required to read from a sub-address that is different from the TDP158 internal sub-address, a write operation with only a sub-address specified is needed before performing the read operation.
Refer to Section 7.5.1 for TDP158 local I2C register descriptions. Reads from reserved fields or addresses that are not specified return zeros. The value written to reserved fields must match the value read from the reserved field to not impact device features or performance.