JAJSI70C May   2008  – November 2019 DAC9881

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ブロック図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: AVDD = 5 V
    6. 7.6  Electrical Characteristics: AVDD = 2.7 V
    7. 7.7  Timing Requirements—Standalone Operation Without SDO
    8. 7.8  Timing Requirements—Standalone Operation With SDO and Daisy-Chain Mode
    9. 7.9  Typical Characteristics: AVDD = 5 V
    10. 7.10 Typical Characteristics: AVDD = 2.7 V
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Analog Output
      2. 8.3.2  Reference Inputs
      3. 8.3.3  Output Range
      4. 8.3.4  Input Data Format
      5. 8.3.5  Hardware Reset
      6. 8.3.6  Power-On Reset
        1. 8.3.6.1 Program Reset Value
      7. 8.3.7  Power Down
      8. 8.3.8  Double-Buffered Interface
        1. 8.3.8.1 Load DAC Pin (LDAC)
          1. 8.3.8.1.1 Synchronous Mode
          2. 8.3.8.1.2 Asynchronous Mode
      9. 8.3.9  1.8-V to 5-V Logic Interface
      10. 8.3.10 Power-Supply Sequence
    4. 8.4 Device Functional Modes
      1. 8.4.1 Serial Interface
        1. 8.4.1.1 Input Shift Register
          1. 8.4.1.1.1 Stand-Alone Mode
          2. 8.4.1.1.2 Daisy-Chain Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Bipolar Operation Using the DAC9881
    2. 9.2 Typical Application
      1. 9.2.1 DAC9881 Sample-and-Hold Circuit
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
    3. 9.3 System Example
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

7.8 Timing Requirements—Standalone Operation With SDO and Daisy-Chain Mode

at –40°C to +105°C (unless otherwise noted); see Figure 2 and Figure 3(1)(2)(3)
MIN MAX UNIT
fSCLK Maximum clock frequency 2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD 20 MHz
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD 25 MHz
t1 Minumum CS high time 2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD 50 ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD 30 ns
t2 Delay from CS falling edge to SCLK rising edge 2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD 10 ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD 8 ns
t3 Delay from SCLK falling edge to CS falling edge 2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD 0 ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD 0 ns
t4 SCLK low time 2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD 25 ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD 20 ns
t5 SCLK high time 2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD 25 ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD 20 ns
t6 SCLK cycle time 2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD 50 ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD 40 ns
t7 Delay from SCLK rising edge to CS rising edge 2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD 10 ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD 10 ns
t8 Input data setup time 2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD 5 ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD 5 ns
t9 Input data hold time 2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD 5 ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD 5 ns
t10 Delay from CS falling edge to SDO valid 2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD 15 ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD 10 ns
t11 Delay from SCLK falling edge to SDO valid 2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD 20 ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD 15 ns
t12 SDO data hold from SCLK rising edge 2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD t5 ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD t5 ns
t13 Delay from CS rising edge to SDO high-Z 2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD 8 ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD 5 ns
t14 Delay from CS rising edge to LDAC falling edge 2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD 10 ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD 5 ns
t15 LDAC pulse width 2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD 15 ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD 10 ns
(1) All input signals are specified with tR = tF = 2ns (10% to 90% of IOVDD) and timed from a voltage level of IOVDD / 2.
(2) Specified by design; not production tested.
(3) Sample tested during the initial release and after any redesign or process changes that may affect these parameters.
DAC9881 tim_stand_wo-sdo_bas438.gifFigure 1. Timing Diagram for Standalone Operation Without SDO
DAC9881 tim_stand_w-sdo_bas438.gifFigure 2. Timing Diagram for Standalone Operation With SDO
DAC9881 tim_daisychain_bas438.gifFigure 3. Timing Diagram for Daisy-Chain Mode, Two Cascaded Devices