JAJSP85A December   2023  – February 2025 LMK5C33216A

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Diagrams
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Differential Voltage Measurement Terminology
    2. 7.2 Output Clock Test Configurations
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
      1. 8.2.1 PLL Architecture Overview
      2. 8.2.2 DPLL
        1. 8.2.2.1 Independent DPLL Operation
        2. 8.2.2.2 Cascaded DPLL Operation
        3. 8.2.2.3 APLL Cascaded With DPLL
      3. 8.2.3 APLL-Only Mode
    3. 8.3 Feature Description
      1. 8.3.1  Oscillator Input (XO)
      2. 8.3.2  Reference Inputs
      3. 8.3.3  Clock Input Interfacing and Termination
      4. 8.3.4  Reference Input Mux Selection
        1. 8.3.4.1 Automatic Input Selection
        2. 8.3.4.2 Manual Input Selection
      5. 8.3.5  Hitless Switching
        1. 8.3.5.1 Hitless Switching With Phase Cancellation
        2. 8.3.5.2 Hitless Switching With Phase Slew Control
        3. 8.3.5.3 Hitless Switching With 1PPS Inputs
      6. 8.3.6  Gapped Clock Support on Reference Inputs
      7. 8.3.7  Input Clock and PLL Monitoring, Status, and Interrupts
        1. 8.3.7.1 XO Input Monitoring
        2. 8.3.7.2 Reference Input Monitoring
          1. 8.3.7.2.1 Reference Validation Timer
          2. 8.3.7.2.2 Frequency Monitoring
          3. 8.3.7.2.3 Missing Pulse Monitor (Late Detect)
          4. 8.3.7.2.4 Runt Pulse Monitor (Early Detect)
          5. 8.3.7.2.5 Phase Valid Monitor for 1PPS Inputs
        3. 8.3.7.3 PLL Lock Detectors
        4. 8.3.7.4 Tuning Word History
        5. 8.3.7.5 Status Outputs
        6. 8.3.7.6 Interrupt
      8. 8.3.8  PLL Relationships
        1. 8.3.8.1  PLL Frequency Relationships
          1. 8.3.8.1.1 APLL Phase Frequency Detector (PFD) and Charge Pump
          2. 8.3.8.1.2 APLL VCO Frequency
          3. 8.3.8.1.3 DPLL TDC Frequency
          4. 8.3.8.1.4 DPLL VCO Frequency
          5. 8.3.8.1.5 Clock Output Frequency
        2. 8.3.8.2  Analog PLLs (APLL1, APLL2, APLL3)
        3. 8.3.8.3  APLL Reference Paths
          1. 8.3.8.3.1 APLL XO Doubler
          2. 8.3.8.3.2 APLL XO Reference (R) Divider
        4. 8.3.8.4  APLL Feedback Divider Paths
          1. 8.3.8.4.1 APLL N Divider With Sigma-Delta Modulator (SDM)
        5. 8.3.8.5  APLL Loop Filters (LF1, LF2, LF3)
        6. 8.3.8.6  APLL Voltage-Controlled Oscillators (VCO1, VCO2, VCO3)
          1. 8.3.8.6.1 VCO Calibration
        7. 8.3.8.7  APLL VCO Clock Distribution Paths
        8. 8.3.8.8  DPLL Reference (R) Divider Paths
        9. 8.3.8.9  DPLL Time-to-Digital Converter (TDC)
        10. 8.3.8.10 DPLL Loop Filter (DLF)
        11. 8.3.8.11 DPLL Feedback (FB) Divider Path
      9. 8.3.9  Output Clock Distribution
      10. 8.3.10 Output Source Muxes
      11. 8.3.11 Output Channel Muxes
      12. 8.3.12 Output Dividers (OD)
      13. 8.3.13 SYSREF/1PPS Output
      14. 8.3.14 Output Delay
      15. 8.3.15 Clock Output Drivers
        1. 8.3.15.1 Differential Output
        2. 8.3.15.2 LVCMOS Output
      16. 8.3.16 Clock Output Interfacing and Termination
      17. 8.3.17 Glitchless Output Clock Start-Up
      18. 8.3.18 Output Auto-Mute During LOL
      19. 8.3.19 Output Synchronization (SYNC)
      20. 8.3.20 Zero-Delay Mode (ZDM)
      21. 8.3.21 DPLL Programmable Phase Delay
      22. 8.3.22 Time Elapsed Counter (TEC)
        1. 8.3.22.1 Configuring TEC Functionality
        2. 8.3.22.2 SPI as a Trigger Source
        3. 8.3.22.3 GPIO Pin as a TEC Trigger Source
          1. 8.3.22.3.1 An Example: Making a Time Elapsed Measurement Using TEC and GPIO1 as Trigger
        4. 8.3.22.4 TEC Timing
        5. 8.3.22.5 Other TEC Behavior
    4. 8.4 Device Functional Modes
      1. 8.4.1 DPLL Operating States
        1. 8.4.1.1 Free-Run
        2. 8.4.1.2 Lock Acquisition
        3. 8.4.1.3 DPLL Locked
        4. 8.4.1.4 Holdover
      2. 8.4.2 Digitally-Controlled Oscillator (DCO) Frequency and Phase Adjustment
        1. 8.4.2.1 DPLL DCO Control
        2. 8.4.2.2 DPLL DCO Relative Adjustment Frequency Step Size
        3. 8.4.2.3 APLL DCO Frequency Step Size
      3. 8.4.3 APLL Frequency Control
      4. 8.4.4 Device Start-Up
        1. 8.4.4.1 Device Power-On Reset (POR)
        2. 8.4.4.2 PLL Start-Up Sequence
        3. 8.4.4.3 Start-Up Options for Register Configuration
        4. 8.4.4.4 GPIO1 and SCS_ADD Functionalities
        5. 8.4.4.5 ROM Page Selection
        6. 8.4.4.6 ROM Detailed Description
        7. 8.4.4.7 EEPROM Overlay
    5. 8.5 Programming
      1. 8.5.1 Memory Overview
      2. 8.5.2 Interface and Control
        1. 8.5.2.1 Programming Through TICS Pro
        2. 8.5.2.2 SPI Serial Interface
        3. 8.5.2.3 I2C Serial Interface
      3. 8.5.3 General Register Programming Sequence
      4. 8.5.4 Steps to Program the EEPROM
        1. 8.5.4.1 Overview of the SRAM Programming Methods
        2. 8.5.4.2 EEPROM Programming With the Register Commit Method
        3. 8.5.4.3 EEPROM Programming With the Direct Writes Method or Mixed Method
        4. 8.5.4.4 Five MSBs of the I2C Address and the EEPROM Revision Number
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Device Start-Up Sequence
      2. 9.1.2 Power Down (PD#) Pin
      3. 9.1.3 Strap Pins for Start-Up
      4. 9.1.4 Pin States
      5. 9.1.5 ROM and EEPROM
      6. 9.1.6 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
        1. 9.1.6.1 Power-On Reset (POR) Circuit
        2. 9.1.6.2 Power Up From a Single-Supply Rail
        3. 9.1.6.3 Power Up From Split-Supply Rails
        4. 9.1.6.4 Non-Monotonic or Slow Power-Up Supply Ramp
      7. 9.1.7 Slow or Delayed XO Start-Up
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Best Design Practices
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Power Supply Bypassing
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
      3. 9.5.3 Thermal Reliability
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 Clock Tree Architect Programming Software
        2. 10.1.1.2 Texas Instruments Clocks and Synthesizers (TICS) Pro Software
        3. 10.1.1.3 PLLatinum™ Simulation Tool
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

LMK5C33216A LMK5C33216A RGC Package 64-Pin VQFN Top View Figure 5-1 LMK5C33216A RGC Package 64-Pin VQFN Top View
Table 5-1 LMK5C33216A Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
POWER
VDDO_0_1 1 P Power supply for OUT0 and OUT1. Connect to supply; do not leave floating or connect to GND.
VDD_APLL1_XO 8 P Power supply for XO and APLL1. Connect to supply; do not leave floating or connect to GND.
VDDO_2_3 11 P Power supply for OUT2 and OUT3. Connect to supply; do not leave floating or connect to GND.
VDD_APLL2 23 P Power supply for APLL2
VDDO_4_TO_7 28 P Power supply for OUT4 to OUT7
VDD_IN0 33 P Power supply for IN0 DPLL reference
VDD_IN1 37 P Power supply for IN1 DPLL reference
VDD_DIG 41 P Power supply for digital. Connect to supply; do not leave floating or connect to GND.
VDDO_14_15 44 P Power supply for OUT14 and OUT15
VDD_APLL3 47 P Power supply for APLL3 (BAW APLL). Connect to supply; do not leave floating or connect to GND.
VDDO_8_TO_13 55 P Power supply for OUT8 to OUT13
DAP N/A G Ground
CORE BLOCKS (2)
LF1 6 A External loop filter cap for APLL1. Recommended capacitor value is 100nF. Refer to APLL Loop Filters (LF1, LF2, LF3) for more details.
CAP_APLL1 7 A LDO bypass capacitor for APLL1 VCO. Recommended capacitor value is 10µF.
LF2 19 A External loop filter cap for APLL2. Recommended capacitor value is 100nF. Refer to APLL Loop Filters (LF1, LF2, LF3) for more details.
CAP3_APLL2 20 A Internal bias bypass capacitor for APLL2 VCO. Recommended capacitor value is 10µF.
CAP2_APLL2 21 A Internal bias bypass capacitor for APLL2 VCO. Recommended capacitor value is 10µF.
CAP1_APLL2 22 A LDO bypass capacitor for APLL2 VCO. Recommended capacitor value is 10µF.
CAP_DIG 40 A LDO bypass capacitor for Digital Core Logic. Recommended capacitor value is 10uF.
CAP_APLL3 48 A Internal bias bypass capacitor for the BAW APLL. Recommended capacitor value is 10µF.
LF3 49 A External loop filter cap for the BAW APLL. Recommended capacitor value is 470nF. Refer to APLL Loop Filters (LF1, LF2, LF3) for more details.
INPUT BLOCKS
XO 9 I XO/TCXO/OCXO input pin, refer to Oscillator Input (XO) for configuring the internal XO input termination.
IN0_P 34 I Primary reference input to DPLLx or buffered to OUT0 or OUT1. Refer to Reference Inputs for configuring the internal reference input termination.
IN0_N 35 I
IN1_N 38 I Secondary reference input to DPLLx or buffered to OUT0 or OUT1. Refer to Reference Inputs for configuring the internal reference input termination.
IN1_P 39 I
OUTPUT BLOCKS
OUT0_P 2 O Clock Output 0. Sources from DPLL reference inputs, XO, the BAW APLL, APLL2, or APLL1. Supports SYSREF/1-PPS output. Programmable formats: AC-LVPECL, LVDS, HSDS, HCSL, 1.8V LVCMOS, or 2.65V LVCMOS. Refer to Clock Outputs for details on configuring and terminating the outputs.
OUT0_N 3 O
OUT1_N 4 O Clock Output 1. Sources from DPLL reference inputs, XO, the BAW APLL, APLL2, or APLL1. Supports SYSREF/1-PPS output. Programmable formats: AC-LVPECL, LVDS, HSDS, HCSL, 1.8V LVCMOS, or 2.65V LVCMOS. Refer to Clock Outputs for details on configuring and terminating the outputs.
OUT1_P 5 O
OUT2_P 12 O Clock Output 2. Sources from the BAW APLL and APLL2. Programmable formats: AC-LVPECL, LVDS, HSDS, or HCSL. Refer to Clock Outputs for details on configuring and terminating the outputs.
OUT2_N 13 O
OUT3_N 14 O Clock Output 3. Sources from the BAW APLL and APLL2. Programmable formats: AC-LVPECL, LVDS, HSDS, or HCSL. Refer to Clock Outputs for details on configuring and terminating the outputs.
OUT3_P 15 O
OUT5_P 24 O Clock Output 5. Sources from the BAW APLL or APLL2. Supports SYSREF/1-PPS output. Programmable formats: AC-LVPECL, LVDS, HSDS, or HCSL. Refer to Clock Outputs for details on configuring and terminating the outputs.
OUT5_N 25 O
OUT4_N 26 O Clock Output 4. Sources from the BAW APLL or APLL2. Supports SYSREF/1-PPS output. Programmable formats: AC-LVPECL, LVDS, HSDS, or HCSL. Refer to Clock Outputs for details on configuring and terminating the outputs.
OUT4_P 27 O
OUT6_P 29 O Clock Output 6. Sources from the BAW APLL or APLL2. Supports SYSREF/1-PPS output. Programmable formats: AC-LVPECL, LVDS, HSDS, or HCSL. Refer to Clock Outputs for details on configuring and terminating the outputs.
OUT6_N 30 O
OUT7_N 31 O Clock Output 7. Sources from the BAW APLL or APLL2. Supports SYSREF/1-PPS output. Programmable formats: AC-LVPECL, LVDS, HSDS, or HCSL. Refer to Clock Outputs for details on configuring and terminating the outputs.
OUT7_P 32 O
OUT14_P 42 O Clock Output 14. Sources from the BAW APLL, APLL2, and APLL1. Programmable formats: AC-LVPECL, LVDS, HSDS, or HCSL. Refer to Clock Outputs (OUTx_P/N) for details on configuring and terminating the outputs.
OUT14_N 43 O
OUT15_N 45 O Clock Output 15. Sources from the BAW APLL, APLL2, or APLL1. Programmable formats: AC-LVPECL, HSDS, LVDS, or HCSL. Refer to Clock Outputs (OUTx_P/N) for details on configuring and terminating the outputs.
OUT15_P 46 O
OUT8_P 51 O Clock Output 8. Sources from the BAW APLL or APLL2. Supports SYSREF/1-PPS output. Programmable formats: AC-LVPECL, LVDS, HSDS, or HCSL. Refer to Clock Outputs for details on configuring and terminating the outputs.
OUT8_N 52 O
OUT9_N 53 O Clock Output 9. Sources from the BAW APLL or APLL2. Supports SYSREF/1-PPS output. Programmable formats: AC-LVPECL, LVDS, HSDS, or HCSL. Refer to Clock Outputs for details on configuring and terminating the outputs.
OUT9_P 54 O
OUT10_P 56 O Clock Output 10. Sources from the BAW APLL or APLL2. Supports SYSREF/1-PPS output. Programmable formats: AC-LVPECL, LVDS, HSDS, or HCSL. Refer to Clock Outputs for details on configuring and terminating the outputs.
OUT10_N 57 O
OUT11_N 58 O Clock Output 11. Sources from the BAW APLL or APLL2. Supports SYSREF/1-PPS output. Programmable formats: AC-LVPECL, LVDS, HSDS, or HCSL. Refer to Clock Outputs for details on configuring and terminating the outputs.
OUT11_P 59 O
OUT12_P 60 O Clock Output 12. Sources from the BAW APLL or APLL2. Supports SYSREF/1-PPS output. Programmable formats: AC-LVPECL, LVDS, HSDS, or HCSL. Refer to Clock Outputs for details on configuring and terminating the outputs.
OUT12_N 61 O
OUT13_N 62 O Clock Output 13. Sources from the BAW APLL or APLL2. Supports SYSREF/1-PPS output. Programmable formats: AC-LVPECL, LVDS, HSDS, or HCSL. Refer to Clock Outputs for details on configuring and terminating the outputs.
OUT13_P 63 O
LOGIC CONTROL/STATUS
GPIO2(3) 10 I/O, S POR: See ROM Detailed Description
Normal Operation: GPIO input or output
SDIO(4) 16 I/O SPI or I2C Data (SDA)
SCK(4) 17 I SPI or I2C Clock (SCL)
SCS_ADD(3) 18 I, S POR: I2C address select (see GPIO1 and SCS_ADD Functionalities and I2C Serial Interface)
Normal Operation: SPI Chip Select (2-state)
PD# 36 I Device power down (active low), internal 200kΩ pullup to VCC
GPIO0(3) 50 I/O, S POR: See ROM Detailed Description
Normal Operation: GPIO input or output
GPIO1(3) 64 I/O, S POR: See GPIO1 and SCS_ADD Functionalities
Normal Operation: GPIO input or output
(1) P = Power, G = Ground, I = Input, O = Output, I/O = Input or Output, A = Analog, S = Configuration.
(2) Do not apply external stimulus to core pins. These performance critical pins are not designed to meet normal latch up testing compliance levels. For best filtering performance, capacitors must be placed close to the IC.
(3) When 3-level mode is enabled during power supply ramp or when PD# is LOW: internal voltage divider of 555kΩ to VCC and 201kΩ to GND. When 2-level input mode is enabled: internal 408kΩ pulldown to GND.
(4) 670kΩ pullup to internal 2.6V LDO.