SBAA528 February   2022 ADC12QJ1600-Q1 , TPS62912 , TPS62913


  1.   Trademarks
  2. 1Introduction and System Description
    1. 1.1 Introduction
      1. 1.1.1 ADC12QJ1600-Q1 Noise and Ripple Requirements
      2. 1.1.2 Power Supply Requirements for Clocks
      3. 1.1.3 TPS62913 Low-Noise and Low-Ripple Buck Converter
    2. 1.2 Block Diagram
    3. 1.3 Design Considerations
  3. 2Tests and Results
    1. 2.1 Test Methodology
    2. 2.2 Test Conditions
    3. 2.3 Test Results
  4. 3Conclusion
  5. 4References
  6.   A Appendix

Test Conditions

The original design and the new design with the TPS62913 were tested in identical conditions for comparison.

AC or dynamic single tone FFT tests are are made with the analog signal applied to the A/D converter at a specific set of frequencies across the converter’s analog input bandwidth. A signal of -1dB below full scale (or dBFS) is used for these frequency tested at the maximum rated sampling value or 1.6 GSPS. The input supply is 12V nominal, and the ambient temperature is 25 C nominal.

The ADC is operated at the sampling clock frequency of 1.6 GHz, which is derived from an external signal generator. The test results are shown using an external clock to LMK which then feeds into the ADC clock. The device register settings are set per the ADC12QJ1600-Q1 data sheet, using the GUI available on the product page, to JMODE0. The FFT is set to 65536 points with no averaging.