SBAU435 February   2024 ADS127L18

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1  EVM Analog Input Options
    2. 2.2  Power Requirements
    3. 2.3  ADC Connections and Decoupling
    4. 2.4  ADC Input Amplifiers
    5. 2.5  VCOM Buffer
    6. 2.6  Voltage Reference
    7. 2.7  Reference Buffer
    8. 2.8  Clock Tree
    9. 2.9  Serial Interface
    10. 2.10 EEPROM
    11. 2.11 Power Supplies
    12. 2.12 Low Dropout Regulator (LDO)
  9. 3Software
    1. 3.1 Software Description
    2. 3.2 ADS127L18 EVM Software Installation
  10. 4Implementation Results
    1. 4.1 EVM Operation
      1. 4.1.1 Evaluation Setup
      2. 4.1.2 Optional EVM Connections
      3. 4.1.3 EVM Register Settings
      4. 4.1.4 ADC Capture Settings
        1. 4.1.4.1 ADC Configuration
        2. 4.1.4.2 Clocking Configuration
        3. 4.1.4.3 SPI and Data Port Configuration
        4. 4.1.4.4 Filter Configuration
        5. 4.1.4.5 Channel Configuration
      5. 4.1.5 Time Domain Display
      6. 4.1.6 Spectral Analysis Display
      7. 4.1.7 Histogram Analysis Display
  11. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layouts
    3. 5.3 Bill of Materials (BOM)
  12. 6Additional Information
    1. 6.1 Trademarks
  13. 7Related Documentation
    1. 7.1 Supplemental Content

2.9 Serial Interface

Figure 3-9 shows the digital connections between the ADS127L18EVM and the PHI. The ADS127L18 ADC uses SPI serial communication in mode 1 (CPOL = 0, CPHA = 1) to configure the internal registers and a Frame-Sync Data Port for conversion data. Because the serial clock (SCLK) frequency and data clock (DCLK) frequency can be as fast as 32.768MHz, the ADS127L18EVM offers 10Ω resistors between the digital signals to aid with signal integrity. Typically, in high-speed SPI and Frame-Sync communication, fast signal edges can cause overshoot; these 10Ω resistors slow down the signal edges to minimize signal overshoot. Headers J3, J4, and J5 provides test points to measure the digital signals or to connect the ADS127L18EVM to an FPGA development board.

CAUTION: The maximum operating voltage level for the digital signals on headers J3, J4, and J5 is 1.95V. Exceeding this voltage level or applying a digital signal before the ADS127L18EVM has been powered-up can cause permanent damage to the ADS127L18.
GUID-20240108-SS0I-JJPK-VN53-N5KCJGDBFPGZ-low.svgFigure 2-9 Connections to Digital Signals on PHI and Test Points