4 McASP - External Signals

• Data Pins: McASP may have up to 16 serializers. These serializers are connected to data pins, referred to as AXR pins. They are named as such ("audio transmit/receive" = "AXR") because any McASP data pin can be configured to functions as an input or as an output. Note that if an AXR pin is running as a transmitter, it is necessary to re-initialize the McASP in order to re-configure it as a receiver. Dynamically switching direction during operation is not supported. The McASP data pin hookup is straightforward. Since any McASP AXR pin can be configured for either transmit or receive, the designer is free to choose whichever pins are most convenient for the system.
• Mute Pins: McASP can have up to two mute pins:
• AMUTEIN – This is an input. Some external devices have a mute output pin; such a signal can be connected to AMUTEIN. McASP can be configured to mute I2S output under this condition.
• AMUTE – This is an output that McASP can be configured to drive under specific error conditions. For more details, see the device-specific TRM. Mute pin hookup is also straightforward. Configuration of the AMUTE pin’s behavior takes some planning (see your device-specific TRM), but it is easy to figure out where to connect it. If the downstream device has a mute input pin, that is what AMUTE should be connected to.
• Clock Pins: McASP may have up to six clock pins, all (and any) of which can be generated internally or sourced externally. There are three types of clock signals on McASP: high frequency (AHCLK), bit (ACLK), and frame sync (AFS). However, each has a transmit version (X, for example, AHCLKX) and a receive version(R, for example, AFSR). Every McASP has a receive clocking section and a transmit clocking section. These are sometimes referred to as the receive port and the transmit port, and each clock port constitutes a clock zone. Therefore, each McASP has two potential clock zones. These can be run asynchronously with respect to each other, but in some cases, synchronous operation is appropriate.
• AHCLKX and AHCLKR – These are high-frequency clocks pins, sometimes referred to as master clocks (often referred to on audio codecs as MCLK). McASP uses a master clock for one purpose: to divide it down and generate a bit clock. There are several cases where a master clock is not required.
• ACLKX and ACLKR – These are bit clocks, often referred to on audio devices as BCK. Data is clocked in and out with respect to bit clock edges. Furthermore, much of McASP’s internal logic (state machines, and so forth) runs off of the bit clock, so a bit clock is ALWAYS required.
• AFSX and AFSR – These are the frame sync clocks, often referred to as word clocks, or more commonly as left-right clocks (LRCK). The “left-right” terminology comes from stereo audio in the I2S format, in which the edges of the frame sync clock denote the bits corresponding to the left and right channels. The frame sync clocks run at the audio stream’s sample rate.

The following figure is a simplified representation of McASP’s external signals, omitting the mute pins.