SLAAEO9 October 2024 MSPM0C1103 , MSPM0C1103-Q1 , MSPM0C1104 , MSPM0C1104-Q1 , MSPM0C1105 , MSPM0C1106 , MSPM0C1106-Q1 , MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G1518 , MSPM0G1519 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3518 , MSPM0G3518-Q1 , MSPM0G3519 , MSPM0G3519-Q1 , MSPM0H3216 , MSPM0H3216-Q1 , MSPM0L1105

There are two core power domains in MSPM0 devices: PD1 and PD0.
As shown in Figure 1-1, the PD1 domain includes the CPU subsystem, the SRAM memory, PD1 peripherals, and the PD1 peripheral bus, which runs from MCLK (including the DMA) with a maximum frequency of 80MHz. The peripherals on PD1 peripheral bus are commonly high-speed peripherals, and usually consume high power while working. The PD0 domain includes the PD0 peripherals and PD0 bus segment, which runs from ULPCLK and is connected to low-speed peripherals, such as universal asynchronous receiver/transmitter (UART), inter-integrated circuit (I2C), real-time clock (RTC).
MSPM0 MCUs implement a policy-based power and clock management scheme. And in certain low-power mode, PD1 can be disabled to minimize power consumption and the peripherals connected are also disabled.