SLLA383A February   2018  – August 2022 SN65HVDA100-Q1 , SN65HVDA195-Q1 , TLIN1022-Q1 , TLIN1029-Q1 , TLIN2022-Q1 , TLIN2029-Q1 , TMS320F28P550SJ , TMS320F28P559SJ-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 LIN Specification Progression
    2. 1.2 Workflow Concept
  4. 2Network Architecture
    1. 2.1 General Layout of the LIN Bus
    2. 2.2 Serial Communication Principles
    3. 2.3 Commander-Responder Principle
    4. 2.4 Message Frame Format
  5. 3Physical Layer Requirements
    1. 3.1 Bus Signaling Fundamentals
    2. 3.2 Pullup Values
    3. 3.3 Threshold Values
    4. 3.4 Bit-Rate Tolerance and Timing Requirements
    5. 3.5 Synchronization and Bit Sampling
    6. 3.6 Duty Cycle
  6. 4Filtering, Distance Limitations, Nodes on Bus
    1. 4.1 EMI and Signal Conditioning
    2. 4.2 ESD and Transients
    3. 4.3 Distance and Node Limitations
  7. 5LIN Transceiver Special Functions
    1. 5.1 Low-Power Modes
      1. 5.1.1 Sleep Mode
      2. 5.1.2 Standby Mode
    2. 5.2 Wakeup
      1. 5.2.1 Pin Wakeup
      2. 5.2.2 LIN Wakeup
      3. 5.2.3 Dominant Timeout
  8. 6Advantages and Disadvantages
  9. 7Conclusion
  10. 8Revision History

3.6 Duty Cycle

To ensure that messages sent are interpreted correctly, the LIN bus must meet the correct voltage levels based on the battery supply and these voltages have to be met within the correct bit sampling time of the receiver.

GUID-49732A7F-23C2-49B4-9686-13E07CDDD378-low.gifFigure 3-5 Bus Duty Cycle Requirement

Figure 3-5 is from TLIN1029-Q1 Local Interconnect Network (LIN) Transceiver with Dominant State Timeout, and is referenced from the LIN specification. It defines the bus timing as a requirement for the proper sampling of each bit. This definition is defined so that when transceivers are designed, the duty cycle is not distorted when propagating from TXD to LIN and from LIN to RXD. Because there is no clock signal sent with the messages and the synchronization is based on the synch field, if there is too much duty cycle variation the commander clock or responder clock can also vary. This affects timing for the remainder of that power cycle.