SLUUCY8 December   2023 BQ77307

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Battery Notational Conventions
    3.     Trademarks
    4.     Glossary
  3. 1 Introduction
  4. 2 Device Description
    1. 2.1 Overview
    2. 2.2 Functional Block Diagram
  5. 3 Device Configuration
    1. 3.1 Direct Commands and Subcommands
    2. 3.2 Configuration Using OTP or Registers
    3. 3.3 Data Formats
      1. 3.3.1 Unsigned Integer
      2. 3.3.2 Integer
      3. 3.3.3 Hex
  6. 4 Device Security
  7. 5 Protection Subsystem
    1. 5.1  Protections Overview
    2. 5.2  Protection Evaluation and Detection
    3. 5.3  Protection FET Drivers
    4. 5.4  Cell Overvoltage Protection
    5. 5.5  Cell Undervoltage Protection
    6. 5.6  Short Circuit in Discharge Protection
    7. 5.7  Overcurrent in Charge Protection
    8. 5.8  Overcurrent in Discharge 1 and 2 Protections
    9. 5.9  Current Protection Latch
    10. 5.10 CHG Detector
    11. 5.11 Overtemperature in Charge Protection
    12. 5.12 Overtemperature in Discharge Protection
    13. 5.13 Internal Overtemperature Protection
    14. 5.14 Undertemperature in Charge Protection
    15. 5.15 Undertemperature in Discharge Protection
    16. 5.16 Cell Open Wire Detection
    17. 5.17 Voltage Reference Diagnostic Protection
    18. 5.18 VSS Diagnostic Protection
    19. 5.19 REGOUT Diagnostic Protection
    20. 5.20 LFO Oscillator Integrity Diagnostic Protection
    21. 5.21 Internal Factory Trim Diagnostic Protection
  8. 6 Device Status and Controls
    1. 6.1 0x00 Control Status() and 0x12 Battery Status() Commands
    2. 6.2 Unused VC Cell Input Pins
    3. 6.3 LDOs
    4. 6.4 ALERT Pin Operation
    5. 6.5 TS Pin Operation
    6. 6.6 Device Event Timing
  9. 7 Operational Modes
    1. 7.1 Overview of Operational Modes
    2. 7.2 NORMAL Mode
    3. 7.3 SHUTDOWN Mode
    4. 7.4 CONFIG_UPDATE Mode
  10. 8 I2C Serial Communications
    1. 8.1 I2C Serial Communications Interface
  11. 9 Commands and Subcommands
    1. 9.1 Direct Commands
    2. 9.2 Bit Field Definitions for Direct Commands
      1. 9.2.1  Safety Alert A Register
      2. 9.2.2  Safety Status A Register
      3. 9.2.3  Safety Alert B Register
      4. 9.2.4  Safety Status B Register
      5. 9.2.5  Battery Status Register
      6. 9.2.6  Alarm Status Register
      7. 9.2.7  Alarm Raw Status Register
      8. 9.2.8  Alarm Enable Register
      9. 9.2.9  FET CONTROL Register
      10. 9.2.10 REGOUT CONTROL Register
    3. 9.3 Command-only Subcommands
    4. 9.4 Subcommands with Data
    5. 9.5 Bitfield Definitions for Subcommands
      1. 9.5.1 DEVICE NUMBER Register
      2. 9.5.2 FW VERSION Register
      3. 9.5.3 HW VERSION Register
      4. 9.5.4 SECURITY KEYS Register
      5. 9.5.5 PROT RECOVERY Register
  12. 10Data Memory
    1. 10.1 Settings
      1. 10.1.1 Settings:Configuration
        1. 10.1.1.1  Settings:Configuration:Reserved
        2. 10.1.1.2  Settings:Configuration:Power Config
        3. 10.1.1.3  Settings:Configuration:REGOUT Config
        4. 10.1.1.4  Settings:Configuration:I2C Address
        5. 10.1.1.5  Settings:Configuration:I2C Config
        6. 10.1.1.6  Settings:Configuration:TS Mode
        7. 10.1.1.7  Settings:Configuration:Vcell Mode
        8. 10.1.1.8  Settings:Configuration:Default Alarm Mask
        9. 10.1.1.9  Settings:Configuration:FET Options
        10. 10.1.1.10 Settings:Configuration:Charge Detector Time
      2. 10.1.2 Settings:Protection
        1. 10.1.2.1 Settings:Protection:Enabled Protections A
        2. 10.1.2.2 Settings:Protection:Enabled Protections B
        3. 10.1.2.3 Settings:Protection:DSG FET Protections A
        4. 10.1.2.4 Settings:Protection:CHG FET Protections A
        5. 10.1.2.5 Settings:Protection:Both FET Protections B
        6. 10.1.2.6 Settings:Protection:Cell Open Wire Check Time
    2. 10.2 Protections
      1. 10.2.1 Protections:Cell Voltage
        1. 10.2.1.1 Protections:Cell Voltage:Cell Undervoltage Protection Threshold
        2. 10.2.1.2 Protections:Cell Voltage:Cell Undervoltage Protection Delay
        3. 10.2.1.3 Protections:Cell Voltage:Cell Undervoltage Protection Recovery Hysteresis
        4. 10.2.1.4 Protections:Cell Voltage:Cell Overvoltage Protection Threshold
        5. 10.2.1.5 Protections:Cell Voltage:Cell Overvoltage Protection Delay
        6. 10.2.1.6 Protections:Cell Voltage:Cell Overvoltage Protection Recovery Hysteresis
      2. 10.2.2 Protections:Current
        1. 10.2.2.1  Protections:Current:Overcurrent in Charge Protection Threshold
        2. 10.2.2.2  Protections:Current:Overcurrent in Charge Protection Delay
        3. 10.2.2.3  Protections:Current:Overcurrent in Discharge 1 Protection Threshold
        4. 10.2.2.4  Protections:Current:Overcurrent in Discharge 1 Protection Delay
        5. 10.2.2.5  Protections:Current:Overcurrent in Discharge 2 Protection Threshold
        6. 10.2.2.6  Protections:Current:Overcurrent in Discharge 2 Protection Delay
        7. 10.2.2.7  Protections:Current:Short Circuit in Discharge Protection Threshold
        8. 10.2.2.8  Protections:Current:Short Circuit in Discharge Protection Delay
        9. 10.2.2.9  Protections:Current:Latch Limit
        10. 10.2.2.10 Protections:Current:Recovery Time
      3. 10.2.3 Protections:Temperature
        1. 10.2.3.1  Protections:Temperature:Overtemperature in Charge Protection Threshold
        2. 10.2.3.2  Protections:Temperature:Overtemperature in Charge Protection Delay
        3. 10.2.3.3  Protections:Temperature:Overtemperature in Charge Protection Recovery
        4. 10.2.3.4  Protections:Temperature:Undertemperature in Charge Protection Threshold
        5. 10.2.3.5  Protections:Temperature:Undertemperature in Charge Protection Delay
        6. 10.2.3.6  Protections:Temperature:Undertemperature in Charge Protection Recovery
        7. 10.2.3.7  Protections:Temperature:Overtemperature in Discharge Protection Threshold
        8. 10.2.3.8  Protections:Temperature:Overtemperature in Discharge Protection Delay
        9. 10.2.3.9  Protections:Temperature:Overtemperature in Discharge Protection Recovery
        10. 10.2.3.10 Protections:Temperature:Undertemperature in Discharge Protection Threshold
        11. 10.2.3.11 Protections:Temperature:Undertemperature in Discharge Protection Delay
        12. 10.2.3.12 Protections:Temperature:Undertemperature in Discharge Protection Recovery
        13. 10.2.3.13 Protections:Temperature:Internal Overtemperature Protection Threshold
        14. 10.2.3.14 Protections:Temperature:Internal Overtemperature Protection Delay
        15. 10.2.3.15 Protections:Temperature:Internal Overtemperature Protection Recovery
    3. 10.3 Power
      1. 10.3.1 Power:Configuration
        1. 10.3.1.1 Power:Configuration:Voltage CHECK Time
        2. 10.3.1.2 Power:Configuration:Body Diode Threshold
      2. 10.3.2 Power:Shutdown
        1. 10.3.2.1 Power:Shutdown:Shutdown Cell Voltage
        2. 10.3.2.2 Power:Shutdown:Shutdown Stack Voltage
        3. 10.3.2.3 Power:Shutdown:Shutdown Temperature
    4. 10.4 Security
      1. 10.4.1 Security:Settings
        1. 10.4.1.1 Security:Settings:Security Settings
        2. 10.4.1.2 Security:Settings:Full Access Key Step 1
        3. 10.4.1.3 Security:Settings:Full Access Key Step 2
      2. 10.4.2 Data Memory Summary
  13. 11Revision History

5.3 Protection FET Drivers

The BQ77307 integrates low-side CHG and DSG FET drivers, which can directly drive low-side protection NFET transistors. The state of the drivers is reported by the 0x12 Battery Status()[CHG] and [DSG] bits. The device supports both series and parallel FET configurations, providing FET body diode protection when configured for a series FET configuration, if one FET driver is on, and the other FET driver is off. In this case, the DSG driver can be turned on to prevent FET damage if the battery pack is charging while the DSG FET is disabled. Similarly, the CHG driver can be turned on if the pack is discharging while the CHG FET is disabled.

The device can be configured for fully autonomous operation, in which case the device autonomously enables the protection FETs if no enabled protection status fault is present which has been configured to control the FETs, and no host command has been issued to force the FET off. Autonomous mode is enabled by setting the Settings:Configuration:FET Options[FET_EN] or sending the 0x0022 FET Enable() subcommand, which toggles the [FET_EN] bit. If [FET_EN] = 0, the FETs remain disabled until they are manually enabled by command.

Manual FET control is available using the 0x29 FET Control() command independent of the setting of [FET_EN]. The format of the 0x29 FET Control() command is shown below. The bits that force the FETs to be enabled are only available if the Settings:Configuration:FET Options[HOST_FETON_EN] is set, while the bits that force the FETs to be disabled are only available if the Settings:Configuration:FET Options[HOST_FETOFF_EN] is set.

Table 5-6 Format for 0x29 FET Control() Command
Bit Name Description
7-4 RSVD Reserved
3 CHG_OFF

CHG FET driver control. This bit only operates if the [HOST_FETOFF_EN] bit in data memory is set.

0x0 = CHG FET driver is allowed to turn on if other conditions are met.

0x1 = CHG FET driver is forced off.
2 DSG_OFF

DSG FET driver control. This bit only operates if the [HOST_FETOFF_EN] bit in data memory is set.

0x0 = DSG FET driver is allowed to turn on if other conditions are met.

0x1 = DSG FET driver is forced off.
1 CHG_ON

CHG FET driver control. This bit only operates if the [HOST_FETON_EN] bit in data memory is set.

0x0 = CHG FET driver is allowed to turn on if other conditions are met.

0x1 = CHG FET driver is forced on.
0 DSG_ON

DSG FET driver control. This bit only operates if the [HOST_FETON_EN] bit in data memory is set.

0x0 = DSG FET driver is allowed to turn on if other conditions are met.

0x1 = DSG FET driver is forced on.

Note that body diode protection takes priority over the manual FET commands. If the user does not want body diode protection to take effect in this case, it can be disabled by clearing the Settings:Configuration:FET Options[SFET] data memory configuration bit.

The BQ77307 provides an option for the device to autonomously disable the CHG FET when current is detected below the body diode threshold. The DSG FET can remain enabled in this mode (based on configuration), but the CHG FET can be disabled to reduce the power flowing through the gate-source resistor around the CHG FET when current is low. When a significant charging or discharging current is detected, the body diode protection then causes the CHG FET to be re-enabled unless other conditions prevent it. The state of the CHG FET in this low current mode is set by the Settings:Configuration:FET Options[CHGOFF] data memory configuration bit.