SLVSJM6 November 2025 MSPM0G5187
UNICOMMI2CT Module
Functional
TSTART flag gets set before the SR.ADDRMATCH in 7 bit mode
On the UNICOMMI2CT bus, the RIS.TSTART flag is set three bus clock cycles before the SR.ADDRMATCH status updates. However, if the interval between the assertion of TSTART and the CPU's read operation of ADDRMATCH exceeds two UNICOMMI2CT clock cycles, the CPU may read a stale ADDRMATCH value, potentially causing an error.