To support IEEE-1588 PTP or other clock steering applications, each DPLL allows precise frequency and phase adjustments through register, or pin control, by using a Digitally-Controlled Oscillator (DCO), as shown in Figure 3-2. Adjustments with less than 1ppt (part per trillion) frequency resolution are supported by the DPLL DCO. The DPLL DCO feature allows increments and decrements to the numerator of the DPLL fractional N-divider. Such frequency adjustments are effectively propagated through the APLL domain and onto the output clocks or any cascaded DPLL/APLL domains.

Figure 3-2 Overview of the DPLL DCO