SNAA396 February   2024 LMK5B33216 , LMK5B33414

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 800G Market Trend
  5. 2LMK5B33216 for SerDes Applications
    1. 2.1 BAW Technology in LMK5B33216
  6. 3LMK5B33216 for Ethernet Applications
    1. 3.1 Frequency and Phase Adjustments
    2. 3.2 Input Reference Switching
    3. 3.3 Holdover
    4. 3.4 Zero-Delay Mode
  7. 4LMK5B33216 Performance
    1. 4.1 Phase Noise Profile
    2. 4.2 RMS Jitter
  8. 5Summary
  9. 6References

5 Summary

The role of clocks are critical in supporting the high-speed data links using the 112G PAM-4 SerDes. Clocks must deliver low jitter and phase noise signals to maintain integrity of the PAM-4 symbols and minimize errors. TI’s BAW technology enables network synchronizer designs with greater system noise margins (primarily the LMK5B33216) which meets the stringent SerDes jitter and phase noise requirements.

Precise frequency and phase adjustments are possible with integrated DCOs and this supports IEEE-1588 PTP designs. The network synchronizer outputs can be configured to lock between different domains (including SyncE and PTP) and hitless switching can occur between references with minimal disturbance to the downstream clocks. The LMK5B33216 leverages a DPLL history feature which sets frequency accuracy to minimize the short-term holdover errors in the event reference clocks are lost.