3 LMK5B33216 Overview

Bit error rates (BER) are minimized in applications involving high-speed SerDes links with the excellent jitter performance of the LMK5B33216. The LMK5B33216, along with the TI PTP Stack option, achieves better than Class D accuracy with sub 5ns timing accuracy. The device is compliant with the ITU-T G.8373.2 standard using the G8275.1 and G8275.2 profiles for full timing and partial timing support (see the application note, LMK5XXXXXS1 Network Synchronizer Compliance Test Report for PTP Profiles G.8275.1 and G.8275.2). For more information on TI’s complete IEEE-1588 PTP and SyncE clocking options, visit TI's Clocks and Timing page.

TI’s network synchronizers leverage a Digital Phase-Locked Loop (DPLL) and an Analog Phase-Locked Loop (APLL) combination to maintain phase lock with a reference clock. The DPLL steers the clock output phase by making continuous updates to the APLL numerator as the DPLL tracks the phase of the reference clock. The LMK5B33216 contains three pairs of DPLL + APLL to support up to three synchronization and frequency domains.

The clock outputs can phase-lock between either two inputs (LMK5B33216) or four inputs (LMK5B33414) when using the DPLL + APLL pair. Alternatively, the outputs can lock to a single reference, or oscillator, when using only the APLL. The device can operate in three modes: normal operation with the DPLL active, holdover when the input clocks are unavailable, and free-run where the DPLL is turned off and only the internal APLL is functioning.

Additionally, the LMK5B33216 provides input clock detection and monitoring, wander and jitter filtering, hitless switching, holdover, and Zero-Delay Mode (ZDM) functionality. Each DPLL includes a programmable loop bandwidth (LBW) to maximize flexibility and ease of use, which can be set between 1MHz to 4kHz without external loop filter components. For SyncE input clocks, TI recommends setting the DPLL LBW between 1Hz and 3Hz to filter out SyncE transient noise. The APLL loop filter is also fully integrated except for one external capacitor.

The LMK5B33216 clock outputs are configurable from several output formats: 1.8V or 2.65V LVCMOS, HCSL, and AC-LVPECL, AC-CML, or LVDS using the High Swing Differential Signaling (HSDS) driver. The output swing and common-mode voltage are programmable to meet various receiver requirements with the HSDS format.