Clocks & timing

Optimize system-level performance with our clocks and timing devices

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Get the best performance from your designs with our portfolio of low-jitter, easy-to-use clocks and timing devices. Build your clock tree with simple, discrete devices or highly integrated solutions that help solve your system timing needs. Learn how our devices enable industry-leading performance in a variety of applications.

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Design & development resources

Design tool
Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.

Application software & framework
Texas Instruments Clocks and Synthesizers (TICS) Pro Software

Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.

Application software & framework
Texas Instruments PLLatinum Simulator Tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

Make complex designs easy with TI clocks

Network synchronizers with BAW VCO for wireless communications and Ethernet-based networking

We designed our high-performance network synchronizers and jitter cleaners to meet stringent jitter cleaning, wander attenuation, reference clock generation and hitless switching requirements.
  • Targeted for ethernet based and wireless networking. 56G/112G/224G PAM-4 SerDes for ethernet-based networking, 4G/5G macro, AAS, RRU, BBU core modules & small cell wireless communications. 
  • Industry leading timing accuracies. Use an Ethernet physical layer reference, GPS or other stable reference to provide ultra-low jitter clocks with precise time- and phase-aligned frequency outputs compliant with Synchronous Ethernet standards, with better than Class-D (<5 ns) timing accuracy.
Featured products for PTP
LMK5C33216 ACTIVE Ultra-low jitter clock synchronizer with JESD204B for wireless communications with BAW
LMK05318B ACTIVE Ultra-low jitter single channel network synchronizer clock with BAW
NEW LMK5B33216 ACTIVE 16-output, three DPLL and APLL, network synchronizer with integrated 2.5-GHz bulk-acoustic-wave VCO

Clocking solutions that enable synchronized interfacing between data converters and FPGAs

We designed our portfolio of high-performance radio-frequency phase-locked loops (PLLs) and synthesizers, JESD204-compliant high-frequency clock distribution products, and multifunctional jitter cleaners and synchronizers to meet clocking requirements for JESD204B and JESD204C applications.
  • Generate phase synchronous clocks. Our devices include features such as system reference (SYSREF) generation, phase sync, output clock-phase adjustment, input-to-output zero-delay modes and SYSREF widowing to enable precise timing between gigahertz clocks and SYSREFs.
  • Ultra-low noise. Our PLLs, equipped with multi-core VCOs, external VCO support and external phase-detector support, help meet the most stringent phase-noise requirements.
User guide
How to Phase Synchronize Multiple LMX2820 Devices
Explains the theory of phase synchronization with LMX2820, the limitations of phase synchronization, and demonstrates how to set up synchronization in a step-by-step guide
Application note
LMX1204 Multiplier Clock Distribution Drives Large Phased-Array Systems
Describes how to distribute a low phase-noise clock or local oscillator (LO) signal across many channels and also how to employ an integrated multiplier operating between 3.2- and 6.4-GHz output

PCIe clocks and timing: generations 1 to 6

Peripheral Component Interconnect Express (PCIe) applications have expanded far beyond the original PC market to include data centers, vehicles and communication networks. Our PCIe products provide basic functions such as clock-generator functionality, zero-delay and fanout buffers, and clock multiplexing functionality.

  • Efficient. Clock generators have a flexible supply rail that supports both 1.8- and 3.3-V core and output supply voltages, with a typical power consumption of 0.5 W.
  • Precise. Clock buffers offer glitch-free control logic and contain fail-safe inputs while running longer traces in common clock architectures with low propagation delay and tightly controlled output-to-output skew of the Intel DB2000QL clock device.
Featured products for PCIe applications
CDCE6214-Q1 ACTIVE Ultra-low power clock generator supporting PCIe gen 1-5 with 2 inputs, 4 outputs and internal EEPROM
CDCDB400 ACTIVE 4-output clock buffer for PCIe® Gen 1 to Gen 6

Technical resources

Video series
Video series
TI Precision Labs - Clocks & Timing videos
Develop your clocks and timing expertise with our comprehensive curriculum of training videos that cover key topics from fundamental terminology and factors of system noise to more advanced design considerations.
Application note
Application note
Multi-Clock Synchronization
Learn how to synchronize multiple devices by either a divider reset, 0-delay, or combination of both methods.
document-pdfAcrobat PDF
Technical article
Technical article
How to select an optimal clocking solution for your FPGA-based design
Learn more about the key factors in choosing a clocking solution for FPGA-based applications.