SNAU246A June   2020  – January 2021 LMX2820

 

  1. 1Trademarks
  2. 2LMX2820EVM Evaluation Module
    1. 2.1 Evaluation Module Contents
    2. 2.2 Evaluation Setup Requirement
    3. 2.3 Resources
  3. 3Setup
    1. 3.1 Connection Diagram
    2. 3.2 Power Supply
    3. 3.3 Reference Clock
    4. 3.4 RF Output
    5. 3.5 Programming
    6. 3.6 Evaluation Software
  4. 4Typical Measurement
    1. 4.1 Default Configuration
      1. 4.1.1 Loop Filter
      2. 4.1.2 Typical Output
    2. 4.2 Additional Tests
      1. 4.2.1 SYSREF Example
      2. 4.2.2 Offset Mixing With PFDIN Pin
      3. 4.2.3 External VCO Mode
      4. 4.2.4 Register Readback
  5. 5Schematic
  6. 6PCB Layout and Layer Stack-Up
    1. 6.1 PCB Layer Stack-Up
    2. 6.2 PCB Layout
  7. 7Bill of Materials
  8. 8Troubleshooting Guide
    1.     A Using Different Reference Clock
      1.      B USB2ANY Firmware Upgrade
        1.       C Revision History

4.2.2 Offset Mixing With PFDIN Pin

The LMX2820 supports offset mxing with PFDIN pin. In this mode, the internal N divider is bypassed.

When using offset mixing with PFDIN pin, the phase detector must operate with a single PFD. As a result, the charge pump current is equal to half the current setting made in register CPG.

GUID-87605171-8E0A-40D4-A324-609FC3CC6CA8-low.png Figure 4-4 Offset Mixing With PFDIN Pin Setting