SNAU287 November   2023

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
  6. 2Hardware
    1. 2.1 Evaluation Setup Requirement
    2. 2.2 Configuring the EVM
      1. 2.2.1 Configuring the Power Supply
      2. 2.2.2 Configuring the Control Pins
      3. 2.2.3 Configuring the Clock Outputs
      4. 2.2.4 Using the USB Interface Connection
      5. 2.2.5 EVM Quick Start Guide
    3. 2.3 Modes of Operation
  7. 3Software
    1. 3.1 Using TICS Pro with the LMK3H0102EVM
      1. 3.1.1 Using the LMK3H0102 Wizard
        1. 3.1.1.1 Frequency Plan
        2. 3.1.1.2 Output Formats
        3. 3.1.1.3 Output Enable Pin
        4. 3.1.1.4 OTP Options
        5. 3.1.1.5 Review
        6. 3.1.1.6 Design Report
      2. 3.1.2 Live Debugger
        1. 3.1.2.1 FODs
        2. 3.1.2.2 Outputs
        3. 3.1.2.3 Others
      3. 3.1.3 Programming
        1. 3.1.3.1 Registers
        2. 3.1.3.2 OTP Configuration
      4. 3.1.4 Help
        1. 3.1.4.1 Contact TI
    2. 3.2 Using TI’s USB2ANY Module for In-System Programming of the LMK3H0102
      1. 3.2.1 USB2ANY Board Connections
      2. 3.2.2 Ordering a USB2ANY Module
  8. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layout
    3. 4.3 Bill of Materials
  9. 5Additional Information
    1.     Trademarks
  10. 6Related Documentation

3.1.2.2 Outputs

GUID-20230927-SS0I-XC8L-C540-0NBHWBJHMKXR-low.pngFigure 3-10 LMK3H0102 Outputs Page

The Outputs page allows for configuration of the channel dividers and output drivers. Before changing any settings on this page, click the Powerdown checkbox, modify the desired settings, then click the Powerdown checkbox again. Either channel divider can be driven from either FOD. Each output driver can be sourced from the respective channel divider, or the Edge Combiner. Output Driver 1 can be sourced from either channel divider output, allowing for power savings if OUT0 and OUT1 are the same frequency. The REF_CTRL pin can be configured as a CLK_READY signal, pulled low, high impedance, or an additional LVCMOS clock sourced from either FOD.

For LP-HCSL outputs, the output swing is adjustable between 625 mV and 950 mV depending on the application requirements. The output can be AC-coupled and used to mimic AC-coupled versions of other clock formats, such as LVPECL. All differential output formats have adjustable slew rate control. LVCMOS clock outputs can be individually enabled, in phase, or 180 degrees out of phase - TI recommends keeping the P and N outputs out of phase unless necessary for improved performance. The text to the right of each output driver summarizes the output frequency, the enable state of the output, and the output format.