SNAU288 December   2023 LMX1906-SP

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 Setup
      1. 2.1.1 Evaluation Setup Requirement
      2. 2.1.2 Connection Diagram
        1. 2.1.2.1 How to Enable Full SPI Control
      3. 2.1.3 Power Requirements
      4. 2.1.4 Pin Mode Strapping
      5. 2.1.5 Reference Clock
        1. 2.1.5.1 Output Connections
        2. 2.1.5.2 Header Information
        3. 2.1.5.3 Default Configuration
        4. 2.1.5.4 How to Generate SYSREF
        5. 2.1.5.5 Multiplier Mode Example
        6. 2.1.5.6 Divider Mode Example
        7. 2.1.5.7 Hybrid Mode: SPI and Pin Mode
  8. 3Software
    1. 3.1 Software Installation
    2. 3.2 Software Description
    3. 3.3 USB2ANY Interface
  9. 4Implementation Results
    1. 4.1 Buffer, Divider, and Multiplier Modes
    2. 4.2 SYSREF Generation
    3. 4.3 SYSREF Delay Generators
  10. 5Hardware Design Files
    1. 5.1 Schematic
    2. 5.2 PCB Layout
      1. 5.2.1 PCB Layer Stack-Up
    3. 5.3 Bill of Materials
  11. 6Additional Information
    1. 6.1 Troubleshooting Guide
      1. 6.1.1 General Guidance
      2. 6.1.2 If Output Is Not Seen on CLKOUT
      3. 6.1.3 If Device Features Are Not Active
      4. 6.1.4 If Multiplier Frequency Is Not Accurate
      5. 6.1.5 If Divider Frequency Is Not Accurate
      6. 6.1.6 If SYSREF Is Not Observed
    2. 6.2 Trademarks

PCB Layout

GUID-20230913-SS0I-QTFQ-MLQG-1ZFDPVD31GDR-low.svg Figure 5-7 Top Layer
GUID-20230913-SS0I-QVGP-H7MZ-3WXG1QPPTCFB-low.svg Figure 5-8 Layer 2 (RF GND)
GUID-20230913-SS0I-MT1L-WNJ3-FP4WQL4R4ZHL-low.svg Figure 5-9 Layer 3 (Power)
GUID-20230913-SS0I-HNPR-1PL1-0MFD0NSCWTZ2-low.svg Figure 5-10 Layer 4 (Power)
GUID-20230913-SS0I-SRLG-TGCB-GGWHCVSHP6VK-low.svg Figure 5-11 Layer 5 (GND)
GUID-20230913-SS0I-VDXZ-LT98-5RFTP4ZK90JG-low.svg Figure 5-12 Bottom Layer