SNAU288 December   2023 LMX1906-SP

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 Setup
      1. 2.1.1 Evaluation Setup Requirement
      2. 2.1.2 Connection Diagram
        1. 2.1.2.1 How to Enable Full SPI Control
      3. 2.1.3 Power Requirements
      4. 2.1.4 Pin Mode Strapping
      5. 2.1.5 Reference Clock
        1. 2.1.5.1 Output Connections
        2. 2.1.5.2 Header Information
        3. 2.1.5.3 Default Configuration
        4. 2.1.5.4 How to Generate SYSREF
        5. 2.1.5.5 Multiplier Mode Example
        6. 2.1.5.6 Divider Mode Example
        7. 2.1.5.7 Hybrid Mode: SPI and Pin Mode
  8. 3Software
    1. 3.1 Software Installation
    2. 3.2 Software Description
    3. 3.3 USB2ANY Interface
  9. 4Implementation Results
    1. 4.1 Buffer, Divider, and Multiplier Modes
    2. 4.2 SYSREF Generation
    3. 4.3 SYSREF Delay Generators
  10. 5Hardware Design Files
    1. 5.1 Schematic
    2. 5.2 PCB Layout
      1. 5.2.1 PCB Layer Stack-Up
    3. 5.3 Bill of Materials
  11. 6Additional Information
    1. 6.1 Troubleshooting Guide
      1. 6.1.1 General Guidance
      2. 6.1.2 If Output Is Not Seen on CLKOUT
      3. 6.1.3 If Device Features Are Not Active
      4. 6.1.4 If Multiplier Frequency Is Not Accurate
      5. 6.1.5 If Divider Frequency Is Not Accurate
      6. 6.1.6 If SYSREF Is Not Observed
    2. 6.2 Trademarks

4.2 SYSREF Generation

The SYSREF generation circuit includes a SYSREF pre-divider and post-divider, a pulser with programmable pulse quantity, and a repeater mode bypass. The SYSREF generator modes re-time the SYSREF signal to the output clock, verifying the SYSREF output is close to the falling edge of the clock output with default delay settings. Repeater mode timing is solely determined by the propagation delay of the device.

To activate the SYSREF generation circuit, the following conditions must be satisfied:

  • SRREQ_MODE field must be set to SYSREFREQ mode.
  • SYSREF_MODE field must be set to the appropriate condition: Continuous, Pulser, or Repeater.
  • In generator modes (continuous or pulser), FINTERPOLATOR % FSYSREF = 0 must be verified.
  • SYSREF_DLY_BYP field must be configured appropriately for generator or repeater modes (a GUI autoset condition normally verifies this whenever SYSREF_MODE is set).
  • SRREQ_VCM field must be set to DC-coupled mode for continuous or pulsed generator output. In repeater mode output, the SYSREF input can be AC- or DC-coupled and SRREQ_VCM must be set accordingly.
  • For continuous mode, a HIGH signal must be seen on SYSREFREQ pins continuously. For pulsed generator mode, a LOW→HIGH transition must be seen on SYSREFREQ pins to trigger the pulser. For repeater mode, the output follows the input state.
GUID-20231114-SS0I-BBLJ-KNBG-DZCC7TXX6Q0S-low.pngFigure 4-5 800-MHz Buffer Mode With 10 MHz SYSREF