SNIU028D February 2016 – September 2020 UCD3138 , UCD3138064 , UCD3138064A , UCD3138128 , UCD3138A , UCD3138A64
Address 0x0008_0028 – Front End Control 2 Pre-Bias Control Register 0
Address 0x000B_0028 – Front End Control 1 Pre-Bias Control Register 0
Address 0x000E_0028 – Front End Control 0 Pre-Bias Control Register 0
17 | 16 | 15 | 8 | 7 | 0 |
PRE_BIAS _POL | PRE_BIAS_EN | PRE_BIAS_RANGE | PRE_BIAS_LIMIT |
R/W-0 | R/W-0 | R/W-1111 1111 | R/W-0000 0000 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
17 | PRE_BIAS_POL | R/W | 0 | Configures polarity of received error voltage 0 = Error equals Vref-Vin (Default) 1 = Error equals Vin-Vref |
16 | PRE_BIAS_EN | R/W | 0 | Enable Pre-Biasing of Error ADC (Ramp should be disabled during pre-biasing, bit 0 of Ramp Control Register) 0 = Pre-Biasing has not been initiated (Default) 1 = Pre-Biasing by hardware has been enabled |
15-8 | PRE_BIAS _RANGE | R/W | 1111 1111 | Sets the acceptable range around the zero error point. If Error ADC value stays in range for number of samples specified by PRE_BIAS_LIMIT (Bits 7:0), PREBIAS_STATUS (Bit 0 of Ramp Status Register) is enabled. Range will be +/- PRE_BIAS_RANGE around zero error point. |
7-0 | PRE_BIAS_LIMIT | R/W | 0000 0000 | Sets the acceptable number of samples in which the Error ADC value stays in range before asserting PREBIAS_STATUS (Bit 0 of Ramp Status Register). Counter limit ranges from 0 to 255. If PREBIAS_STATUS is set, it will take PRE_BIAS_LIMIT samples outside of acceptable range before clearing PREBIAS_STATUS. |