SNLA293 May   2022 DP83TC811R-Q1 , DP83TC811S-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Hardware Configuration
    1. 2.1 Schematic
  4. 3Software Configuration
  5. 4Testing PMA
    1. 4.1 PMA Testing Procedure
  6. 5Testing IOP: Link-up and Link-down
    1. 5.1 IOP Testing Procedure
  7. 6Testing SQI
    1. 6.1 SQI Testing Procedure
    2. 6.2 SQI Mapping with Link Quality
  8. 7Testing TDR
    1. 7.1 TDR Testing Procedure
  9. 8Testing EMC/EMI
  10. 9Revision History

3 Software Configuration

This section contains the register settings of DP83TC811 used during tests in different OA compliance test houses. Most of these register settings are added to optimize performance during OA & EMC/EMI testing. It is recommended to implement these register settings as part for initialization for all DP83TC811 applications. Other application specific features offered by DP83TC811 can be adjusted via hardware or software configurations.

Table 3-1 Master Mode Configuration
MMD Register Optimized Description
0x1F 0x0475 0x0008 To not let the PHY link-up until config is done
0x1F 0x0485 0x11FF DSP settings for margins during OA, EMI tests
0x1F 0x0462 0x0600 Disable unused LED_1 on the board
0x1F 0x010F 0x0100 DSP settings for margins during OA, EMI tests
0x1F 0x0410 0x6000 DSP settings for margins during OA, EMI tests
0x1F 0x0479 0x0442 DSP settings for margins during OA, EMI tests
0x1F 0x0466 0x8000 DSP settings for margins during OA, EMI tests
0x1F 0x0107 0x2605 DSP settings for margins during OA, EMI tests
0x1F 0x0106 0xB8BB DSP settings for margins during OA, EMI tests
0x1F 0x0116 0x03CA DSP settings for margins during OA, EMI tests
0x1F 0x0114 0xC00A DSP settings for margins during OA, EMI tests
0x1F 0x010B 0x0700 DSP settings for margins during OA, EMI tests
0x1F 0x0132 0x01EE DSP settings for margins during OA, EMI tests
0x1F 0x04DE 0x03F0 DSP settings for margins during OA, EMI tests
0x1F 0x003E 0x000D DSP settings for margins during OA, EMI tests
0x1F 0x0111 0x6009 DSP settings for margins during OA, EMI tests
0x1F 0x0129 0x009F DSP settings for margins during OA, EMI tests
0x1F 0x04D5 0xFEA4 DSP settings for margins during OA, EMI tests
0x1F 0x04D6 0x0EA4 DSP settings for margins during OA, EMI tests
0x1F 0x0120 0x0067 DSP settings for margins during OA, EMI tests
0x1F 0x0125 0x7A56 DSP settings for margins during OA, EMI tests
0x1F 0x0461 0x0408 Tune IO impedance with board traces
0x1F 0x0400 0x1300 MDI termination optimization
0x1F 0x0403 0x0030 MDI transmission optimization
0x1F 0x0404 0x0008 MDI transmission optimization
0x1F 0x048A 0x0D02 DSP settings for margins during OA, EMI tests
0x1F 0x048B 0x350F DSP settings for margins during OA, EMI tests
0x1F 0x048C 0x0033 DSP settings for margins during OA, EMI tests
0x1F 0x048D 0x010D DSP settings for margins during OA, EMI tests
0x1F 0x0121 0x1500 DSP settings for margins during OA, EMI tests
0x1F 0x0122 0x1000 DSP settings for margins during OA, EMI tests
0x1F 0x04D4 0x7522 DSP settings for margins during OA, EMI tests
0x1F 0x0130 0xC720 DSP settings for margins during OA, EMI tests
0x1F 0x0126 0x0515 DSP settings for margins during OA, EMI tests
0x1F 0x0119 0x00A4 DSP settings for margins during OA, EMI tests
0x1F 0x0109 0x095D DSP settings for margins during OA, EMI tests
0x1F 0x010E 0x3219 DSP settings for margins during OA, EMI tests
0x1F 0x010C 0x1996 DSP settings for margins during OA, EMI tests
0x1F 0x001F 0x4000 Soft reset
0x1F 0x0475 0x0000 Let the PHY link-up
Table 3-2 Slave Mode Configuration
MMD Register Optimized Description
0x1F 0x0475 0x0008 To not let the PHY link-up until config is done
0x1F 0x0485 0x11FF DSP settings for margins during OA, EMI tests
0x1F 0x0462 0x0600 Disable unused LED_1 on the board
0x1F 0x010F 0x0100 DSP settings for margins during OA, EMI tests
0x1F 0x0410 0x6000 DSP settings for margins during OA, EMI tests
0x1F 0x0479 0x0442 DSP settings for margins during OA, EMI tests
0x1F 0x0466 0x8000 DSP settings for margins during OA, EMI tests
0x1F 0x0107 0x2605 DSP settings for margins during OA, EMI tests
0x1F 0x0106 0xB8BB DSP settings for margins during OA, EMI tests
0x1F 0x0116 0x03CA DSP settings for margins during OA, EMI tests
0x1F 0x0114 0xC00A DSP settings for margins during OA, EMI tests
0x1F 0x010B 0x0700 DSP settings for margins during OA, EMI tests
0x1F 0x0132 0x01EE DSP settings for margins during OA, EMI tests
0x1F 0x04DE 0x03F0 DSP settings for margins during OA, EMI tests
0x1F 0x003E 0x000D DSP settings for margins during OA, EMI tests
0x1F 0x0111 0x6009 DSP settings for margins during OA, EMI tests
0x1F 0x0129 0x009F DSP settings for margins during OA, EMI tests
0x1F 0x04D5 0xFEA4 DSP settings for margins during OA, EMI tests
0x1F 0x04D6 0x0EA4 DSP settings for margins during OA, EMI tests
0x1F 0x0120 0x0067 DSP settings for margins during OA, EMI tests
0x1F 0x0125 0x7A56 DSP settings for margins during OA, EMI tests
0x1F 0x0461 0x0408 Tune IO impedance with board traces
0x1F 0x0400 0x1300 MDI termination optimization
0x1F 0x0403 0x0030 MDI transmission optimization
0x1F 0x0404 0x0008 MDI transmission optimization
0x1F 0x048A 0x0D02 DSP settings for margins during OA, EMI tests
0x1F 0x048B 0x350F DSP settings for margins during OA, EMI tests
0x1F 0x048C 0x0033 DSP settings for margins during OA, EMI tests
0x1F 0x048D 0x010D DSP settings for margins during OA, EMI tests
0x1F 0x0121 0x1500 DSP settings for margins during OA, EMI tests
0x1F 0x0122 0x1450 DSP settings for margins during OA, EMI tests
0x1F 0x04D4 0x7322 DSP settings for margins during OA, EMI tests
0x1F 0x0130 0xC780 DSP settings for margins during OA, EMI tests
0x1F 0x0126 0x0495 DSP settings for margins during OA, EMI tests
0x1F 0x0115 0x8AC8 DSP settings for margins during OA, EMI tests
0x1F 0x0109 0x095D DSP settings for margins during OA, EMI tests
0x1F 0x010E 0xFAFB

DSP settings for margins during OA, EMI tests.

Value can be changed to x7DFB if further reduction in link-up time is required
0x1F 0x010C 0x19FA DSP settings for margins during OA, EMI tests
0x1F 0x0101 0x2082 DSP settings for margins during OA, EMI tests
0x1F 0x001F 0x4000 Soft reset
0x1F 0x0475 0x0000 Let the PHY link-up
Note: Sequence of above register writes is important. For both master and slave configuration all the DSP settings are in-between the writes to register 0x0475. This is to make sure that the link-up sequence does not start before the full configuration is written.