5 Exception Vector Table

Exceptions are interruptions of the normal program flow. The Cortex-R4/5 processor usually takes care to preserve the critical parts of the current processor state, so that the normal program flow could be resumed after the exception was handled by the application (saving and restoring of the CPSR and banked Stack Pointers).

The processor state (ARM/Thumb2) and the operating mode can and will change on exception entry. The Cortex-R4/5 processor supports exception entry in ARM and in Thumb2 state, the default after reset as implemented in the Hercules family is the ARM state. The default state is used in this bootloader example.

When the hardware takes an exception, the program counter (PC) is automatically set to the address of the relevant exception vector and the microcontroller begins executing instructions from that address. When the microcontroller comes out of reset, the PC is automatically set to 0x00000000. An undefined instruction sets the PC to 0x00000004, and a data abort sets the PC to 0x00000010, and so forth.

The exception table for ARM Cortex-R devices is held in flash and cannot be modified easily. The reset vector must always point to the start of the bootloader code (0x00000000). One solution is to have an exception service routine (UNDEF, SWI, DABT, PABT) in the bootloader that redirect to the exception vector table located at a fixed location within the application memory space. Using this method added one indirect jump instruction to each exception handler resulting in extra processor load for each interrupt that is processed. Because the content of the IRQ/FIQ interrupt vector registers from the VIM are loaded into PC at 0x18/0x1C of exception vector table, there is no need to redirect IRQ/FIQ.

Another solution is to use the exception handlers in the application. When any exception (UNDEF, SWI, DABT, PABT) occurs, processor fetches the handler address from 0x04/0x08/0x0C/0x10, and jumps to the handler in application. To achieve this, the branch addresses in bootloader exception vector table need to be changed to Application Start Address – 0x8 in ARM state, and Application Start Address – 0x4 in Thumb2 state.

;***************************************************************************** .sect ".intvecs" ;------------------------------------------------------------------------------- ; import reference for interrupt routines .ref _c_int00 ;------------------------------------------------------------------------------- ; interrupt vectors ; application start address is 0x10020 b _c_int00 ;0x00 b #0x10018 ;0x04 UNDEF; application start address - 0x08 b #0x10018 ;0x08 SVC ; application start address - 0x08 b #0x10018 ;0x0C PABT ; application start address - 0x08 b #0x10018 ;0x10 DABT ; application start address - 0x08 reservedEntry b reservedEntry ;0x14 ldr pc,[pc, #-0x1b0] ;0x18 ldr pc,[pc, #-0x1b0] ;0x1C

This bootloader example does not use any interrupt. There is no exception handler for UNDEF, SWI, DABT, and PABT in this bootloader example.